search_path = ". /usr/designs/Library/RO35/EXD/synopsys/"
link_library = "ROHM035_lin.db ROHM035IO_lin.db" 
target_library = "ROHM035_lin.db ROHM035IO_lin.db"
symbol_library = ""
default_schematic_options = "-size infinite" 
read -format verilog {"cnt.v"} 
create_schematic -size infinite    -gen_database  
check_design 
set_port_is_pad all_inputs() 
set_port_is_pad all_outputs() 
set_pad_type -exact RZIBUF all_inputs() 
set_pad_type -exact RZOBUF all_outputs() 
set_pad_type -exact RZIOBUF find( port "DIO*" ) 
insert_pads -respect_hierarchy

derive_timing_constraints -max_delay_scale 1.00 -min_delay_scale 1.00 -period_scale 1.0
current_design "Counter" 
set_operating_conditions TYPICAL
compile  -map_effort high  -boundary_optimization  

report_cell 
report_area 
report_timing -path full -delay max -max_paths 1 -nworst 1 -to all_registers(-data_pins) + all_outputs() 
write -format db -hierarchy -output cnt.db

verilogout_no_tri = true 
verilogout_single_bit = false
write -format  verilog -hierarchy -output cntSyn.v
report_cell -nosplit -connections -verbose > CellInfo.log