1 cmCreateLib 2 setFormField "Create Library" "Library Name" "CNT" 3 setFormField "Create Library" "Technology File Name" "/usr/designs/Library/ROHM/EXD/avanti/rohm06apollo.tf" 4 formOK "Create Library"
同様に配置配線IOライブラリ
を指定フルパスで指定
以上でOKをクリック。
5 cmRefLib 6 setFormField "Ref Library" "Library Name" "CNT" 7 setFormField "Ref Library" "Ref Library Name" "/usr/designs/Library/ROHM/EXD/avanti/ROHM06LIN" 8 formApply "Ref Library" 9 setFormField "Ref Library" "Ref Library Name" "/usr/designs/Library/ROHM/EXD/avanti/ROHM06IOLIN" 10 formOK "Ref Library"
11 cmShowRefLib 12 setFormField "Show Ref Libraries" "Library Name" "CNT" 13 formOK "Show Ref Libraries"
14 auVerilogIn 15 setFormField "Verilog In Data File" "Library Name" "CNT" 16 setFormField "Verilog In Data File" "Verilog File Name" "cntout.v" 17 setFormField "Verilog In Data File" "Bus Naming Style" "\[%d\]" 18 formOK "Verilog In Data File"
19 cmCmdExpand 20 setFormField "Expand Netlist" "Library Name" "cnt" 21 setFormField "Expand Netlist" "Unexpanded Cell Name" "counter.netl" 22 setFormField "Expand Netlist" "Expanded Cell Name" "cntexp.netl" 23 formOK "Expand Netlist"
24 menuQuit 25 formYes "Dialog Box"