search_path = ". /usr/designs/Library/ROHM/EXD/synopsys/" 
link_library = "rohm06_lin.db RohmIO_lin.db" 
target_library = "rohm06_lin.db RohmIO_lin.db" 
symbol_library = "" 
default_schematic_options = "-size infinite" 
read -format verilog {"cnt.v"} 
create_schematic -size infinite    -gen_database  
check_design 
set_port_is_pad all_inputs() 
set_port_is_pad all_outputs() 
set_pad_type -exact RZIBUFB all_inputs() 
set_pad_type -exact RZOBUF all_outputs() 
set_pad_type -exact RZIOBUFB find( port "DIO*" ) 
insert_pads  -respect_hierarchy

current_design "Counter" 
compile  -map_effort high  -boundary_optimization  

report_cell 
report_area 
report_timing -path full -delay max -max_paths 1 -nworst 1 -to all_registers(-data_pins) + all_outputs() 
write -format db -hierarchy -output cnt.db

verilogout_no_tri = true 
verilogout_single_bit = false
write -format  verilog -hierarchy -output cntout.v
report_cell -nosplit -connections -verbose > CellInfo.log