--
-- add16.vhd
-- Described by Tohru Ishihara
--
library IEEE;
library EXD;
use IEEE.std_logic_1164.all;
use EXD.all;
entity add16 is
end add16;
architecture gate_level of add16 is
component OAI21
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component AOI21B
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component NOR21
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND21
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR2
port( A, B : in std_logic; Y : out std_logic);
end component;
component AOI21
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component XOR2
port( A, B : in std_logic; Y : out std_logic);
end component;
component EOR
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component XNOR2
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND2
port( A, B : in std_logic; Y : out std_logic);
end component;
component OAI211
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component NAND22
port( A, B : in std_logic; Y : out std_logic);
end component;
component NOR22
port( A, B : in std_logic; Y : out std_logic);
end component;
component NAND43
port( A, B, C, D : in std_logic; Y : out std_logic);
end component;
component GEN3
port( A, B, C, D, E, F, G : in std_logic; Y : out std_logic);
end component;
component NAND32
port( A, B, C : in std_logic; Y : out std_logic);
end component;
component INV1
port( A : in std_logic; Y : out std_logic);
end component;
signal n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15,
n16, n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28,
n29, n30, n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41,
n42, n43, n44, n45, n46, n47, n48, n49, n50, n51, n52, n53, n54,
n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67,
n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79
: std_logic;
SIGNAL A, B : std_logic_vector (15 downto 0);
SIGNAL CI : std_logic;
SIGNAL SUM : std_logic_vector (15 downto 0);
SIGNAL CO : std_logic;
begin
U1 : OAI21 port map( A => n3, B => n1, C => n2, Y => CO);
U2 : AOI21B port map( A => n7, B => n6, C => n5, Y => n4);
U3 : NOR21 port map( A => n10, B => n9, Y => n8);
U4 : NAND21 port map( A => n13, B => n12, Y => n11);
U5 : AOI21B port map( A => n17, B => n16, C => n15, Y => n14);
U6 : NOR21 port map( A => n17, B => n16, Y => n18);
U7 : NAND21 port map( A => n21, B => n20, Y => n19);
U8 : NOR21 port map( A => n24, B => n23, Y => n22);
U9 : NOR2 port map( A => n7, B => n5, Y => n25);
U10 : NOR2 port map( A => n27, B => n28, Y => n26);
U11 : NOR21 port map( A => n1, B => n3, Y => n29);
U12 : NOR2 port map( A => n31, B => n32, Y => n30);
U13 : NOR21 port map( A => n35, B => n34, Y => n33);
U14 : NOR2 port map( A => n37, B => n38, Y => n36);
U15 : NOR21 port map( A => n41, B => n40, Y => n39);
U16 : NOR2 port map( A => n43, B => n44, Y => n42);
U17 : AOI21 port map( A => n31, B => n45, C => n46, Y => n2);
U18 : XOR2 port map( A => n47, B => n8, Y => SUM(9));
U19 : EOR port map( A => n48, B => n11, C => n48, D => n11, Y => SUM(8));
U20 : XOR2 port map( A => n49, B => n14, Y => SUM(7));
U21 : XNOR2 port map( A => n15, B => n18, Y => SUM(6));
U22 : XNOR2 port map( A => n50, B => n51, Y => SUM(5));
U23 : EOR port map( A => n52, B => n19, C => n52, D => n19, Y => SUM(4));
U24 : XOR2 port map( A => n53, B => n22, Y => SUM(3));
U25 : XNOR2 port map( A => n54, B => n25, Y => SUM(2));
U26 : XOR2 port map( A => n55, B => n26, Y => SUM(1));
U27 : XNOR2 port map( A => n56, B => n29, Y => SUM(15));
U28 : XOR2 port map( A => n57, B => n30, Y => SUM(14));
U29 : XNOR2 port map( A => n58, B => n33, Y => SUM(13));
U30 : XOR2 port map( A => n59, B => n36, Y => SUM(12));
U31 : XOR2 port map( A => n60, B => n39, Y => SUM(11));
U32 : XNOR2 port map( A => n61, B => n42, Y => SUM(10));
U33 : NAND2 port map( A => A(0), B => B(0), Y => n62);
U34 : NAND2 port map( A => A(12), B => B(12), Y => n63);
U35 : EOR port map( A => CI, B => n64, C => CI, D => n64, Y => SUM(0));
U36 : NOR2 port map( A => n66, B => n67, Y => n65);
U37 : NAND2 port map( A => A(8), B => B(8), Y => n13);
U38 : NAND2 port map( A => A(4), B => B(4), Y => n21);
U39 : AOI21B port map( A => n38, B => n59, C => n37, Y => n58);
U40 : OAI211 port map( A => n23, B => n69, C => n24, D => n4, Y => n68);
U41 : OAI21 port map( A => n21, B => n52, C => n20, Y => n51);
U42 : OAI21 port map( A => n62, B => n66, C => n67, Y => n55);
U43 : NOR2 port map( A => A(8), B => B(8), Y => n12);
U44 : NAND22 port map( A => A(7), B => B(7), Y => n70);
U45 : NOR22 port map( A => A(7), B => B(7), Y => n71);
U46 : NAND22 port map( A => A(6), B => B(6), Y => n16);
U47 : NOR22 port map( A => A(6), B => B(6), Y => n17);
U48 : NAND22 port map( A => A(5), B => B(5), Y => n72);
U49 : NOR22 port map( A => A(5), B => B(5), Y => n73);
U50 : NOR2 port map( A => A(4), B => B(4), Y => n20);
U51 : NOR2 port map( A => A(3), B => B(3), Y => n24);
U52 : NAND2 port map( A => A(3), B => B(3), Y => n23);
U53 : NOR2 port map( A => A(2), B => B(2), Y => n5);
U54 : NAND2 port map( A => A(2), B => B(2), Y => n74);
U55 : NOR2 port map( A => A(1), B => B(1), Y => n28);
U56 : NAND2 port map( A => A(1), B => B(1), Y => n75);
U57 : OAI21 port map( A => n75, B => n28, C => n62, Y => n6);
U58 : NOR2 port map( A => A(0), B => B(0), Y => n66);
U59 : NAND43 port map( A => n65, B => n24, C => n28, D => n5, Y => n69);
U60 : GEN3 port map( A => n71, B => n70, C => n17, D => n16, E => n73, F =>
n51, G => n72, Y => n76);
U61 : NAND22 port map( A => A(9), B => B(9), Y => n9);
U62 : NOR22 port map( A => A(9), B => B(9), Y => n10);
U63 : AOI21 port map( A => n73, B => n51, C => n72, Y => n15);
U64 : NAND21 port map( A => n70, B => n71, Y => n49);
U65 : NAND21 port map( A => n72, B => n73, Y => n50);
U66 : AOI21B port map( A => n27, B => n55, C => n28, Y => n54);
U67 : OAI21 port map( A => n74, B => n5, C => n54, Y => n53);
U68 : NOR2 port map( A => A(14), B => B(14), Y => n32);
U69 : NOR2 port map( A => A(13), B => B(13), Y => n35);
U70 : NOR2 port map( A => A(12), B => B(12), Y => n37);
U71 : NAND22 port map( A => A(11), B => B(11), Y => n40);
U72 : NOR22 port map( A => A(11), B => B(11), Y => n41);
U73 : NOR2 port map( A => A(10), B => B(10), Y => n44);
U74 : NAND2 port map( A => A(10), B => B(10), Y => n77);
U75 : OAI21 port map( A => n13, B => n12, C => n48, Y => n47);
U76 : GEN3 port map( A => n41, B => n40, C => n43, D => n78, E => n10, F =>
n47, G => n9, Y => n59);
U77 : NAND2 port map( A => A(13), B => B(13), Y => n34);
U78 : OAI21 port map( A => n34, B => n58, C => n35, Y => n57);
U79 : NOR22 port map( A => A(14), B => B(14), Y => n31);
U80 : AOI21 port map( A => n31, B => n46, C => n57, Y => n56);
U81 : NOR2 port map( A => A(15), B => B(15), Y => n1);
U82 : NAND2 port map( A => A(15), B => B(15), Y => n3);
U83 : AOI21 port map( A => n10, B => n47, C => n9, Y => n61);
U84 : OAI21 port map( A => n77, B => n44, C => n61, Y => n60);
U85 : NOR21 port map( A => n66, B => n62, Y => n64);
U86 : NAND32 port map( A => n59, B => n35, C => n37, Y => n79);
U87 : OAI211 port map( A => n34, B => n79, C => n35, D => n63, Y => n45);
U88 : INV1 port map( A => CI, Y => n67);
U89 : INV1 port map( A => n63, Y => n38);
U90 : INV1 port map( A => n68, Y => n52);
U91 : INV1 port map( A => n74, Y => n7);
U92 : INV1 port map( A => n75, Y => n27);
U93 : INV1 port map( A => n76, Y => n48);
U94 : INV1 port map( A => n32, Y => n46);
U95 : INV1 port map( A => n44, Y => n78);
U96 : INV1 port map( A => n77, Y => n43);
PROCESS
BEGIN
A <= "0000000000000000";
B <= "1111111111111111";
CI <= '0';
wait for 50 ns;
CI <= '1';
wait;
END PROCESS;
end gate_level;
CONFIGURATION SIM_MODEL OF add16 IS -- entity のあとのなまえ
FOR gate_level -- Architecrute のあとのなまえ
END FOR;
END SIM_MODEL;