LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE WORK.pkg_kue2.all;

ENTITY alu IS 
   PORT (cf      : IN  std_logic;
         a       : IN  logic8;
         b       : IN  logic8;
         ope     : IN  logic4;
         aluo    : OUT logic7;
         ov      : OUT std_logic;
         cr      : OUT std_logic;
         ng      : OUT std_logic;
         zr      : OUT std_logic);
END alu;

ARCHITECTURE alu_body OF alu IS
   SIGNAL alu_mode : ArithType;
   SIGNAL ans      : logic9;
BEGIN
   alu_mode <= alu_decode(ope);

   PROCESS (alu_mode,a,b,cf)
   BEGIN
      CASE alu_mode IS
         WHEN A_SBC  => ans <= add_sub(('0' & a), ('0' & b), cf,  FALSE);
         WHEN A_ADC  => ans <= add_sub(('0' & a), ('0' & b), cf,  TRUE);
         WHEN A_SUB  => ans <= add_sub(('0' & a), ('0' & b), '0', FALSE);
         WHEN A_ADD  => ans <= add_sub(('0' & a), ('0' & b), '0', TRUE);
         WHEN A_EOR  => ans <= ('0' & a) XOR ('0' & b);
         WHEN A_OR   => ans <= ('0' & a) OR  ('0' & b);
         WHEN A_AND  => ans <= ('0' & a) AND ('0' & b);
         WHEN OTHERS => ans <= "XXXXXXXXX";
      END CASE;
   END PROCESS;

   PROCESS (a,b,ans,alu_mode)
   BEGIN
      CASE alu_mode IS
         WHEN A_ADC | A_ADD => 
            IF ((a(7) = b(7)) AND (a(7) /= ans(7))) THEN
               ov <= '1';
            ELSE
               ov <= '0';
            END IF;
         WHEN A_SBC | A_SUB =>
            IF ((a(7) /= b(7)) AND (b(7) = ans(7))) THEN
               ov <= '1';
            ELSE
               ov <= '0';
            END IF;
         WHEN OTHERS => ov <= 'X';
      END CASE; 
   END PROCESS;

   zr_ng: PROCESS (ans)
   BEGIN
      IF (ans(7 DOWNTO 0) = "00000000") THEN
         zr <= '1';
      ELSE
         zr <= '0';
      END IF; 
   END PROCESS;

   cr   <= ans(8);
   ng   <= ans(7);
   aluo <= ans(6 DOWNTO 0);
END alu_body;