LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE WORK.pkg_kue2.all;

ENTITY alu_block IS 
   PORT (clock   : IN  std_logic;
         reset   : IN  std_logic;
         alud    : IN  logic8;
         dbo     : IN  logic8;
         c_alu   : IN  std_logic;
         alu_ope : IN  logic4;
         c_acc   : IN  logic4;
         c_ix    : IN  logic4;
         c_reg   : IN  logic3;
         flag_ob : IN  std_logic;
         cfset   : IN  logic3;
         vfset   : IN  logic3;
         nfset   : IN  logic3;
         zfset   : IN  logic3;
         ob      : OUT logic8;
         flag    : OUT logic4;
         aluo    : OUT logic8;
         dbi     : OUT logic8);
END alu_block;

ARCHITECTURE arith_body OF alu_block IS
   COMPONENT reg
      PORT (clock   : IN std_logic;
            reset   : IN std_logic;
            cf      : IN std_logic;
            reg     : IN logic3;
            control : IN logic4;
            in_reg  : IN logic8;
            out_reg : OUT logic8;
            dbi_out : OUT logic8;
            ob      : OUT logic8;
            tcr     : OUT std_logic);
   END COMPONENT;
   COMPONENT sel8
      PORT (a  : IN logic8;
            b  : IN logic8;
            sl : IN std_logic;
            st : IN std_logic;
            y  : OUT logic8);
   END COMPONENT;
   COMPONENT alu
      PORT (cf      : IN std_logic;
            a       : IN logic8;
            b       : IN logic8;
            ope     : IN logic4;
            aluo    : OUT logic7;
            ov      : OUT std_logic;
            cr      : OUT std_logic;
            ng      : OUT std_logic;
            zr      : OUT std_logic);
   END COMPONENT;
   COMPONENT status
      PORT (clock   : IN std_logic;
            reset   : IN std_logic;
            alu_ov  : IN std_logic;
            alu_cr  : IN std_logic;
            alu_ng  : IN std_logic;
            alu_zr  : IN std_logic;
            acc_tcr : IN std_logic;
            ix_tcr  : IN std_logic;
            flag_ob : IN std_logic;
            cfset   : IN logic3;
            vfset   : IN logic3;
            nfset   : IN logic3;
            zfset   : IN logic3;
            flag    : OUT logic4;
            ob      : OUT logic8);
   END COMPONENT;      
   SIGNAL acc_out : logic8;
   SIGNAL acc_tcf : std_logic;
   SIGNAL ix_out  : logic8;
   SIGNAL ix_tcf  : std_logic;
   SIGNAL alu_a   : logic8;
   SIGNAL aluout  : logic7;
   SIGNAL alu_ov  : std_logic;
   SIGNAL alu_cr  : std_logic;
   SIGNAL alu_zr  : std_logic;
   SIGNAL alu_ng  : std_logic;
   SIGNAL stable  : std_logic;
   SIGNAL f_tmp   : logic4;
BEGIN
   U_acc_reg : reg PORT MAP (clock   => clock,
                                        reset   => reset,
                                        cf      => f_tmp(3),
                                        reg     => c_reg,
                                        control => c_acc,
                                        IN_reg  => dbo,
                                        OUT_reg => acc_out,
                                        dbi_out => dbi,
                                        ob      => ob,
                                        tcr     => acc_tcf);

    U_ix_reg : reg PORT MAP (clock   => clock,
                                        reset   => reset,
                                        cf      => f_tmp(3),
                                        reg     => c_reg,
                                        control => c_ix,
                                        in_reg  => dbo,
                                        out_reg => ix_out,
                                        dbi_out => dbi,
                                        ob      => ob,
                                        tcr     => ix_tcf);

   U_sel : sel8 PORT MAP (a  => acc_out,
                               b  => ix_out,
                               sl => c_alu,
                               st => stable,
                               y  => alu_a);
   
   stable <= not alu_ope(3);

   U_alu : alu PORT MAP (cf   => f_tmp(3),
                               a    => alu_a,
                               b    => alud,
                               ope  => alu_ope,
                               aluo => aluout,
                               ov   => alu_ov,
                               cr   => alu_cr,
                               ng   => alu_ng,
                               zr   => alu_zr);

   U_flags : status PORT MAP (clock   => clock,
                                    reset   => reset,
                                    alu_ov  => alu_ov,
                                    alu_cr  => alu_cr,
                                    alu_ng  => alu_ng,
                                    alu_zr  => alu_zr,
                                    acc_tcr => acc_tcf,
                                    ix_tcr  => ix_tcf,
                                    flag_ob => flag_ob,
                                    cfset   => cfset,
                                    vfset   => vfset,
                                    nfset   => nfset,
                                    zfset   => zfset,
                                    flag    => f_tmp,
                                    ob      => ob);

   aluo <=	alu_ng & aluout;
   flag <= f_tmp;
END arith_body;