LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE WORK.pkg_kue2.all; ENTITY alu_frame IS PORT (clock_p : IN std_logic; reset_p : IN std_logic; alud_p : IN logic8; dbo_p : IN logic8; c_alu_p : IN std_logic; alu_ope_p : IN logic4; c_acc_p : IN logic4; c_ix_p : IN logic4; c_reg_p : IN logic3; flag_ob_p : IN std_logic; cfset_p : IN logic3; vfset_p : IN logic3; nfset_p : IN logic3; zfset_p : IN logic3; ob_p : OUT logic8; flag_p : OUT logic4; aluo_p : OUT logic8; dbi_p : OUT logic8); END alu_frame; ARCHITECTURE frame_body OF alu_frame IS COMPONENT XCTIB00 port( A : IN std_logic; Y : OUT std_logic); end COMPONENT; COMPONENT XCTOB04 port( A : IN std_logic; Y : OUT std_logic); end COMPONENT; COMPONENT alu_block PORT (clock : IN std_logic; reset : IN std_logic; alud : IN logic8; dbo : IN logic8; c_alu : IN std_logic; alu_ope : IN logic4; c_acc : IN logic4; c_ix : IN logic4; c_reg : IN logic3; flag_ob : IN std_logic; cfset : IN logic3; vfset : IN logic3; nfset : IN logic3; zfset : IN logic3; ob : OUT logic8; flag : OUT logic4; aluo : OUT logic8; dbi : OUT logic8); END COMPONENT; SIGNAL clock : std_logic; SIGNAL reset : std_logic; SIGNAL alud : logic8; SIGNAL dbo : logic8; SIGNAL c_alu : std_logic; SIGNAL alu_ope : logic4; SIGNAL c_acc : logic4; SIGNAL c_ix : logic4; SIGNAL c_reg : logic3; SIGNAL flag_ob : std_logic; SIGNAL cfset : logic3; SIGNAL vfset : logic3; SIGNAL nfset : logic3; SIGNAL zfset : logic3; SIGNAL ob : logic8; SIGNAL flag : logic4; SIGNAL aluo : logic8; SIGNAL dbi : logic8; BEGIN ALU_CHIP : alu_block port map(clock => clock, reset => reset, alud => alud, dbo => dbo, c_alu => c_alu, alu_ope => alu_ope, c_acc => c_acc, c_ix => c_ix, c_reg => c_reg, flag_ob => flag_ob, cfset => cfset, vfset => vfset, nfset => nfset, zfset => zfset, ob => ob, flag => flag, aluo => aluo, dbi => dbi); IB0 : XCTIB00 port map(A => clock_p, Y => clock); IB1 : XCTIB00 port map(A => reset_p, Y => reset); IB2 : XCTIB00 port map(A => alud_p(0), Y => alud(0)); IB3 : XCTIB00 port map(A => alud_p(1), Y => alud(1)); IB4 : XCTIB00 port map(A => alud_p(2), Y => alud(2)); IB5 : XCTIB00 port map(A => alud_p(3), Y => alud(3)); IB6 : XCTIB00 port map(A => alud_p(4), Y => alud(4)); IB7 : XCTIB00 port map(A => alud_p(5), Y => alud(5)); IB8 : XCTIB00 port map(A => alud_p(6), Y => alud(6)); IB9 : XCTIB00 port map(A => alud_p(7), Y => alud(7)); IB10 : XCTIB00 port map(A => dbo_p(0), Y => dbo(0)); IB11 : XCTIB00 port map(A => dbo_p(1), Y => dbo(1)); IB12 : XCTIB00 port map(A => dbo_p(2), Y => dbo(2)); IB13 : XCTIB00 port map(A => dbo_p(3), Y => dbo(3)); IB14 : XCTIB00 port map(A => dbo_p(4), Y => dbo(4)); IB15 : XCTIB00 port map(A => dbo_p(5), Y => dbo(5)); IB16 : XCTIB00 port map(A => dbo_p(6), Y => dbo(6)); IB17 : XCTIB00 port map(A => dbo_p(7), Y => dbo(7)); IB18 : XCTIB00 port map(A => c_alu_p, Y => c_alu); IB19 : XCTIB00 port map(A => alu_ope_p(0), Y => alu_ope(0)); IB20 : XCTIB00 port map(A => alu_ope_p(1), Y => alu_ope(1)); IB21 : XCTIB00 port map(A => alu_ope_p(2), Y => alu_ope(2)); IB22 : XCTIB00 port map(A => alu_ope_p(3), Y => alu_ope(3)); IB23 : XCTIB00 port map(A => c_acc_p(0), Y => c_acc(0)); IB24 : XCTIB00 port map(A => c_acc_p(1), Y => c_acc(1)); IB25 : XCTIB00 port map(A => c_acc_p(2), Y => c_acc(2)); IB26 : XCTIB00 port map(A => c_acc_p(3), Y => c_acc(3)); IB27 : XCTIB00 port map(A => c_ix_p(0), Y => c_ix(0)); IB28 : XCTIB00 port map(A => c_ix_p(1), Y => c_ix(1)); IB29 : XCTIB00 port map(A => c_ix_p(2), Y => c_ix(2)); IB30 : XCTIB00 port map(A => c_ix_p(3), Y => c_ix(3)); IB31 : XCTIB00 port map(A => c_reg_p(0), Y => c_reg(0)); IB32 : XCTIB00 port map(A => c_reg_p(1), Y => c_reg(1)); IB33 : XCTIB00 port map(A => c_reg_p(2), Y => c_reg(2)); IB34 : XCTIB00 port map(A => flag_ob_p, Y => flag_ob); IB35 : XCTIB00 port map(A => cfset_p(0), Y => cfset(0)); IB36 : XCTIB00 port map(A => cfset_p(1), Y => cfset(1)); IB37 : XCTIB00 port map(A => cfset_p(2), Y => cfset(2)); IB38 : XCTIB00 port map(A => vfset_p(0), Y => vfset(0)); IB39 : XCTIB00 port map(A => vfset_p(1), Y => vfset(1)); IB40 : XCTIB00 port map(A => vfset_p(2), Y => vfset(2)); IB41 : XCTIB00 port map(A => nfset_p(0), Y => nfset(0)); IB42 : XCTIB00 port map(A => nfset_p(1), Y => nfset(1)); IB43 : XCTIB00 port map(A => nfset_p(2), Y => nfset(2)); IB44 : XCTIB00 port map(A => zfset_p(0), Y => zfset(0)); IB45 : XCTIB00 port map(A => zfset_p(1), Y => zfset(1)); IB46 : XCTIB00 port map(A => zfset_p(2), Y => zfset(2)); OB0 : XCTOB04 port map(A => flag(0), Y => flag_p(0)); OB1 : XCTOB04 port map(A => flag(1), Y => flag_p(1)); OB2 : XCTOB04 port map(A => flag(2), Y => flag_p(2)); OB3 : XCTOB04 port map(A => flag(3), Y => flag_p(3)); OB4 : XCTOB04 port map(A => aluo(0), Y => aluo_p(0)); OB5 : XCTOB04 port map(A => aluo(1), Y => aluo_p(1)); OB6 : XCTOB04 port map(A => aluo(2), Y => aluo_p(2)); OB7 : XCTOB04 port map(A => aluo(3), Y => aluo_p(3)); OB8 : XCTOB04 port map(A => aluo(4), Y => aluo_p(4)); OB9 : XCTOB04 port map(A => aluo(5), Y => aluo_p(5)); OB10 : XCTOB04 port map(A => aluo(6), Y => aluo_p(6)); OB11 : XCTOB04 port map(A => aluo(7), Y => aluo_p(7)); OB12 : XCTOB04 port map(A=>dbi(0), Y=>dbi_p(0)); OB13 : XCTOB04 port map(A=>dbi(1), Y=>dbi_p(1)); OB14 : XCTOB04 port map(A=>dbi(2), Y=>dbi_p(2)); OB15 : XCTOB04 port map(A=>dbi(3), Y=>dbi_p(3)); OB16 : XCTOB04 port map(A=>dbi(4), Y=>dbi_p(4)); OB17 : XCTOB04 port map(A=>dbi(5), Y=>dbi_p(5)); OB18 : XCTOB04 port map(A=>dbi(6), Y=>dbi_p(6)); OB19 : XCTOB04 port map(A=>dbi(7), Y=>dbi_p(7)); OB20 : XCTOB04 port map(A=>ob(0), Y=>ob_p(0)); OB21 : XCTOB04 port map(A=>ob(1), Y=>ob_p(1)); OB22 : XCTOB04 port map(A=>ob(2), Y=>ob_p(2)); OB23 : XCTOB04 port map(A=>ob(3), Y=>ob_p(3)); OB24 : XCTOB04 port map(A=>ob(4), Y=>ob_p(4)); OB25 : XCTOB04 port map(A=>ob(5), Y=>ob_p(5)); OB26 : XCTOB04 port map(A=>ob(6), Y=>ob_p(6)); OB27 : XCTOB04 port map(A=>ob(7), Y=>ob_p(7)); END frame_body;