LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE WORK.pkg_kue2.all; ENTITY status IS PORT (clock : IN std_logic; reset : IN std_logic; alu_ov : IN std_logic; alu_cr : IN std_logic; alu_ng : IN std_logic; alu_zr : IN std_logic; acc_tcr : IN std_logic; ix_tcr : IN std_logic; flag_ob : IN std_logic; cfset : IN logic3; vfset : IN logic3; nfset : IN logic3; zfset : IN logic3; flag : OUT logic4; ob : OUT logic8); END status; ARCHITECTURE status_body OF status IS SIGNAL cf,vf,tcf,next_cf,next_vf,next_tcf : std_logic; SIGNAL nf,zf,next_nf,next_zf : std_logic; BEGIN PROCESS (reset, clock) BEGIN IF (reset = '0') THEN cf <= '0'; vf <= '0'; nf <= '0'; zf <= '0'; tcf <= '0'; ELSIF (clock'EVENT AND clock = '1') THEN cf <= next_cf; vf <= next_vf; nf <= next_nf; zf <= next_zf; tcf <= next_tcf; END IF; END PROCESS; PROCESS (cfset,alu_cr,cf,tcf) BEGIN IF (cfset(2) /= '0') THEN next_cf <= cf; ELSE CASE cfset(1 DOWNTO 0) IS WHEN "00" => next_cf <= '0'; WHEN "01" => next_cf <= '1'; WHEN "10" => next_cf <= alu_cr; WHEN OTHERS => next_cf <= tcf; END CASE; END IF; END PROCESS; PROCESS (vfset,alu_ov,vf,tcf,alu_ng) BEGIN IF (vfset(2) /= '0') THEN next_vf <= vf; ELSE CASE vfset(1 DOWNTO 0) IS WHEN "00" => next_vf <= '0'; WHEN "01" => next_vf <= '1'; WHEN "10" => next_vf <= alu_ov; WHEN OTHERS => next_vf <= tcf XOR alu_ng; END CASE; END IF; END PROCESS; PROCESS (nfset,alu_ng,nf) BEGIN IF (nfset(2) /= '0') THEN next_nf <= nf; ELSE CASE nfset(1 DOWNTO 0) IS WHEN "00" => next_nf <= '0'; WHEN "01" => next_nf <= '1'; WHEN OTHERS => next_nf <= alu_ng; END CASE; END IF; END PROCESS; PROCESS (zfset,alu_zr,zf) BEGIN IF (zfset(2) /= '0') THEN next_zf <= zf; ELSE CASE zfset(1 DOWNTO 0) IS WHEN "00" => next_zf <= '0'; WHEN "01" => next_zf <= '1'; WHEN OTHERS => next_zf <= alu_zr; END CASE; END IF; END PROCESS; PROCESS (acc_tcr, ix_tcr, tcf) BEGIN next_tcf <= acc_tcr OR ix_tcr; END PROCESS; flag <= cf & vf & nf & zf; ob <= tcf & "000" & cf & vf & nf & zf WHEN flag_ob = '0' ELSE "ZZZZZZZZ"; END status_body;