‚PD •ĺWlˆő

y‹łŽöAuŽtA‚Ü‚˝‚͏•‹ł ‚P–ź

‚QD ę–ĺ•Ş–ě

”ź“ą‘ĚÝŒv‹ZpAÝŒvŽx‰‡‹ZpAƒn[ƒhƒEƒFƒAEƒ\ƒtƒgƒEƒFƒA‹Ś’˛ÝŒv‹Zp‚ȂǁA‘ĺ‹K–͏WĎƒVƒXƒeƒ€‚ĚÝŒv‚Ć—˜—p‚ÉŠÖ‚ˇ‚é•Ş–ě‘S”Ę

‚RD Š‘Ž

“Œ‹ž‘ĺŠw‘ĺ‹K–͏WĎƒVƒXƒeƒ€ÝŒv‹łˆçŒ¤‹†ƒZƒ“ƒ^[

‚SD ”CŠú

‚T”Ni”CŠúI—šŽž‚̍ĐR¸‚É‚ć‚čÄ”C‚̉”\Ť‚ ‚čj‚Ü‚˝‚́A‚Č‚ľiĚ—pŽž‚ÉŒˆ’č—\’čj

‚TD ‹Ć–ą“ŕ—e

”ź“ą‘ĚÝŒv‹Zp‚âÝŒvŽx‰‡‹Zp‚ÉŠÖ‚ˇ‚é‹łˆçEŒ¤‹†‚đ’S“–‚ˇ‚éB‚Ü‚˝A‘ĺ‹K–͏WĎƒVƒXƒeƒ€ÝŒv‹łˆçŒ¤‹†ƒZƒ“ƒ^[‚Ş‘S‘‚Ě‘ĺŠwE‚ę‚Č‚Ç‚É’ń‹Ÿ‚ľ‚Ä‚˘‚锟“ą‘ĚÝŒvEť‘˘ƒT[ƒrƒX‚ÉŠÖ‚ˇ‚é‹Ć–ą‚đ‘ź‹łˆőEƒXƒ^ƒbƒt‚Ć‚Ć‚ŕ‚ɐ‹s‚ˇ‚éB

‚UD ‰ž•ĺŽ‘Ši

(1)   ”ŽŽm‚ĚŠwˆĘ‚đ—L‚ľCŒ¤‹†‚Ć‹łˆç‚É”MˆÓ‚Ě‚ ‚é•űB

(2)   ŠÖ˜A‚ˇ‚éę–ĺ•Ş–ě‚Ĺ—D‚ę‚˝Œ¤‹†‹ĆŃ‚Ş‚ ‚čAŠw•”E‘ĺŠw‰@Šwś‚Ě‹łˆçEŽw“ą‚Ş‚Ĺ‚Ť‚é•ű

(3)   ‘ĺ‹K–͏WĎƒVƒXƒeƒ€ÝŒv‹łˆçŒ¤‹†ƒZƒ“ƒ^[‹Ć–ą‚ĚŽďŽ|‚đ—‰đ‚ľA‚ć‚č‚悢ƒT[ƒrƒX’ń‹Ÿ‚É”MˆÓ‚Ě‚ ‚é•ű

‚VD ’…”CŽžŠú

Ě—pŒˆ’čŒăA‚Ĺ‚Ť‚é‚ž‚Ż‘‚˘ŽžŠú

‚WD ‹Î–ą’n

“Œ‹ž‘ĺŠwó–ěƒLƒƒƒ“ƒpƒX“ŕ‘ĺ‹K–͏WĎƒVƒXƒeƒ€ÝŒv‹łˆçŒ¤‹†ƒZƒ“ƒ^[

‚XD ’ńo‘—ށi—lŽŽ‚Í”CˆÓAŠeˆę•”j

 (1) —š—đ‘i—lŽŽ‚ÍŽs”Ě—š—đ‘‚É€‚¸‚é‚ą‚ƁCŽĘ^“\•tjB

 (2) Œ¤‹†‹ĆŃƒŠƒXƒgF¸“Ç•t‚ŤŠwp˜_•śC‘Ű‰ď‹c“™ƒvƒƒV[ƒfƒBƒ“ƒOƒXi¸“ǁu—LE –łv‚đ–ž‹LjC’˜‘C‘ŕE‰đŕC“Á‹–‚É•Ş—Ţ‚ľC‘S’˜ŽŇ–źC‘č–Ú, ŽGŽ–ź, ŠŞ, •Ĺ, ”­ •\”N‚đ‹LÚB‚ť‚Ě‘źCŽóÜ—đCľ‘ҍu‰‰“™C“Á•M‚ˇ‚ׂŤŽ–€

 (3) Žĺ—v˜_•ś‚Ě•Ęü‚či5•ŇˆČ“ŕjŠe1•”iƒRƒs[‚ŕ‰Âj

 (4) ‚ą‚ę‚Ü‚Ĺ‚ĚŒ¤‹†‹ĆŃŠT—vi2000Žš’ö“xj

 (5) Ě—p‚ł‚ę‚˝ę‡‚ĚŒ¤‹†E‹łˆç‚ɑ΂ˇ‚é•ř•‰i2000Žš’ö“xj

 (6) ‰ČŠwŒ¤‹†”ď•â•‹ŕC‹¤“ŻŒ¤‹†ĽŽó‘őŒ¤‹†, ‹Ł‘ˆ“IŽ‘‹ŕ“™‚ĚŠl“žó‹ľiŽ‘‹ŕ–źCŒ¤‹†‰Ű‘č–źC‹ŕŠzCŒ¤‹†ŠúŠÔCŒ¤‹†‘ă•\ŽŇE•Ş’SŽŇ‚Ě•Ę‚đ–ž‹L‚ˇ‚é‚ą‚Ɓj

 (7) ŠŒŠ‚đ‹‚ß“ž‚é•ű2–ź‚ĚŽ–ź‚Ć˜A—ć

‚P‚OD‰ž•ĺYŘ

•˝Ź26”N9ŒŽ1“ú•K’…

‚P‚PD‘—Ţ‘—•tćE–₢‡‚í‚šć

§113-0032 “Œ‹ž“s•ś‹ž‹ć–퐜2-11-16•“cć’[’mƒrƒ‹

“Œ‹ž‘ĺŠw‘ĺ‹K–͏WĎƒVƒXƒeƒ€ÝŒv‹łˆçŒ¤‹†ƒZƒ“ƒ^[Ž––ąŽş ˆś

‰ž•ĺ‘—Ţ‚Í••“›‚Ɂu‘ĺ‹K–͏WĎƒVƒXƒeƒ€ÝŒv‹łˆçŒ¤‹†ƒZƒ“ƒ^[‹łˆő‰ž•ĺ‘—ŢÝ’†v‚ĆŽé‘‚ľAŠČˆŐ‘—Ż‚Ĺ‘—•t‚Ě‚ą‚ƁB‰ž•ĺ‘—Ţ‚Í•Ô‹p‚ľ‚Ü‚š‚ńB

‚Č‚¨A‚˛Žż–â“™‚͏ă‹LŽ––ąŽşA‚Ü‚˝‚Í“Ą“cšGi fujita@ee.t.u-tokyo.ac.jp j‚Ü‚Ĺ‚¨–₢‡‚í‚š‰ş‚ł‚˘B

 

ˆČă

 

For applicant out of Japan:

VLSI Design and Education Center (VDEC) at the University of Tokyo invites applications for a termed or tenure-track faculty position at the Assistant/Associate Professor levels. We seek outstanding persons with strong records of academic accomplishments in research and education as well as willingness to serve for academic VLSI design and fabrication as a member of VDEC. Applicant must hold PhD in engineering or science relating to VLSI design and development. Expertise in EDA (Electronic Design Automation) algorithm development and/or chip design/fabrication experience is preferred. Candidates are expected to establish or keep outstanding records of researches and participate in teaching and supervising undergraduate/graduate students. The position is available now and the deadline of application is the end of August.

Application must be sent by physical mail but applicant should first contact

Masahiro Fujita at fujita@ee.t.u-tokyo.ac.jp

for details of the application procedures as well as the required documents which should be attached to an application.

 Deadline of application: End of August, 2014