平成22年度 VDEC高位設計セミナー
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10:00 | Keynote: Acceleration of Verification and Verification of Acceleration Oskar Mencer (CEO, Maxeler Technologies) |
10:40 | Efficient and Practical Prevention of X-Related Bugs Pranav Ashar (CTO, Real Intent) |
11:20 | Functional Qualification of Verification Environments for Digital Logic Design Bindesh Patel (Technology manager, SpringSoft) |
12:00 | Lunch break |
13:30 | Acceleration of numeric calculations on FPGAs Akira Fukui (Graduate student, The University of Tokyo) |
14:10 | Assertion Synthesis: Enabling Assertion-Based Verification For Simulation, Formal and Emulation Flows Yunshan Zhu (CEO, Nextop) |
14:50 | Mini break |
15:00 | Innovative Efficiencies for Understanding SystemVerilog Testbench Behavior Bindesh Patel (Technology manager, SpringSoft) |
15:40 | What You Need to Know for Effective CDC Verification Pranav Ashar (CTO, Real Intent) |
16:20 | Demo/Poster Sessions (-20:00) |
17:00 | Reception (-20:00) |
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