1st D2T Special Seminar 2021 ONLINE
April 7 Wed. 9:00 am- JST
Zoom online
Language: English
The 1st D2T Special Seminar 2021 ONLINE will be held on April 7 Wednesday 9:00am - JST. we introduce two topics: lectures of FPGA for AI by Dr. Alan Mishchenko and Machine Learning + Electronic Design Automation by Dr. Sat Chatterjee. These two topics are very hot recently. Please join the seminar.
Registration (Free of charge):
Thank you for your attendance. We will announce an on-demand seminar soon.
The seminar uses zoom registration system. If you have questions, please contact D2T office.
Topics:
Chair Person: Akio Higo, Ph.D., d.lab, the University of Tokyo
Talk I
FPGA for AI: General Resource Allocation and Specialized Building Blocks
Dr. Alan Mishchenko, University of California at Berkeley
Abstract
This talk presents resource allocation recommendations for designing FPGAs used to build power-efficient parametrizable neural network accelerators. In order to converge on an "AI-friendly" FPGA, the following questions are addressed: what is a reasonable ratio of LUTs, FFs, DSPs, and BRAMs to be available on FPGAs, and what is a good interconnect structure and IO requirements. The talk also proposes several dedicated hardware blocks for FPGAs meant to accelerate quantized CNNs, including a vectorized traditional DSP unit and a specialized DSP unit for processing numbers with a fixed-bit mantissa and shared exponent designed to match CNN computations. The talk will conclude with a demo video of an FPGA-based accelerator for object detection using a Yolo-style CNN running on Avnet Ultra96-V2 board with Xilinx ZU3EG FPGA.
Biography
Alan graduated with M.S. from Moscow Institute of Physics and Technology (Moscow, Russia) in 1993 and received his Ph.D. from Glushkov Institute of Cybernetics (Kiev, Ukraine) in 1997. In 2002, Alan joined the EECS Department at University of California, Berkeley, where he is currently a full researcher. His research focuses on computationally efficient logic synthesis, formal verification, machine learning, and hardware acceleration.
Chair Person: Takashi Matsumoto, Ph.D., d.lab, the University of Tokyo
Talk II
Machine Learning + Electronic Design Automation for Fun and Profit
Dr. Sat Chatterjee
Google
Abstract
This talk will have two parts. The first part (profit?) will touch on two projects where ideas from Machine Learning (ML) can help with problems in Electronic Design Automation (EDA). The first project is about improving coverage by applying black box optimization methods to tuning test parameters. The second is about a contest we organized at the International Workshop on Logic Synthesis (IWLS) 2020 where the goal was to learn an unknown Boolean function from a set of input/output examples (i.e., a careset). Unlike usual logic synthesis optimization objectives such as minimizing area or delay, the goal of the contest was to maximize generalization (albeit under an area constraint). We believe that this line of research could be useful for approximate logic synthesis particularly in ML applications. The second part (fun?) will be on how methods from EDA, and particularly ideas inspired by FPGA lookup tables, can help answer a fundamental question in deep learning today: Why do neural networks generalize when they have sufficient capacity to memorize their training set.
Biography
Sat is an Engineering Leader and Machine Learning Researcher at Google AI. His current research focuses on fundamental questions in deep learning (such as understanding why neural networks generalize at all) as well as various applications of ML (such as hardware design and verification).
Before Google, he was a Senior Vice President at Two Sigma, a leading quantitative investment manager, where he founded one of the first successful deep learning-based alpha research groups on Wall Street and led a team that built one of the earliest end-to-end FPGA-based trading systems for general purpose ultra-low latency trading. Prior to that, he was a Research Scientist at Intel where he worked on microarchitectural performance analysis and formal verification for on-chip networks.
He did his undergraduate studies at IIT Bombay, has a PhD in Computer Science from UC Berkeley, and has published in the top machine learning, design automation, and formal verification conferences.
Organizer
D2T Research Department, Systems Design Lab, School of Engineering, The University of Tokyo
Platform Device Research Devision, Systems Design Lab, School of Engineering, The University of Tokyo
Contact
Akio Higo
higo"@"if.t.u-tokyo.ac.jp
ADVANTEST D2T Research Department,
Systems Design Lab (d.lab),
School of Engineering, The University of Tokyo
Tel: +81-3-5841-0233 FAX: +81-3-5841-1093