The 3rd D2T Special Seminar 2022 ONLINE
2022.11.11 Fri. 3:30pm- JST

Zoom meeting/Hybrid(学内限定)
Language: English
11月のD2T特別セミナーでは、米国で活躍されている研究者2名による講演を行います。

最初の講演では、従来よりも20%以上回路性能向上が期待できる、最新の論理回路自動合成手法について解説します。従来手法とは異なり、論理最適化処理、回路のテクノロジライブラリのセルからなる回路への変換、そして、組合せ回路を部分的にフリップフロップをこえて移動させることによる順序回路のタイミング最適化が統合されています。この手法はオープンソースツールとして実装され公開されています。
2番目の講演では、深層学習に関する議論の内もっとも興味深い点である、なぜ深層学習結果は個々のトレーニングデータを記憶するだけでなく、それらの知識を一般化できるのか、について議論します。つまり、なぜ見たこともない新しい入力に対しても適切な出力をだせるのか、についてです。講演では、実験結果に基づいた、一般化される機構の新しい説明を提示し、また、今後の方向について議論します。

D2T seminar in November hosts two distinguished researchers from US.

The first talk discusses advanced logic circuit synthesis techniques by which logic circuit operations can become faster by 20% or more. The idea is to unify logic optimization, transformation into cells in libraries, and sequential circuit optimization, and recently implemented new tools significantly improve the performance of the synthesized circuits.

The second talk discusses one of the most important issues in deep learning: why learning results by deep learning have generalization not just memorizing each training pattern. That is, it reasonably works well as well for new inputs which are never seen in the training phase. This is the key feature of deep learning, and the talk gives a way to explain it and proposes future directions.

Free registration:
Register here

After registrating, you will recieve a confirmation e-mail containing information about joining the seminar.
We use the Zoom meeting system. If you don't reach the mail after the registration, please contact D2T research department.

Chairperson: Masahiro Fujita and Akio Higo, (d.lab the Univ. of Tokyo)
Title
Integrating Logic Synthesis, Technology Mapping, and Retiming


Dr. Alan Mishchenko

Abstract
This talk presents a method that combines logic synthesis, technology mapping, and retiming into a single integrated flow. The proposed integrated method is applicable to both standard cell and FPGA designs. An efficient implementation uses sequential And- Inverter Graphs (AIGs). Experiments on a variety of industrial circuits from the IWLS 2005 benchmarks show an average reduction of the clock period of 25%, compared to the traditional mapping without retiming, and by 20%, compared to traditional mapping followed by retiming applied as a post-processing step.

Speaker Bio:
Alan graduated with M.S. from Moscow Institute of Physics and Technology (Moscow, Russia) in 1993 and received his Ph.D. from Glushkov Institute of Cybernetics (Kiev, Ukraine) in 1997. In 2002, Alan joined the EECS Department at University of California, Berkeley, where he is currently a full researcher. His research is in computationally efficient logic synthesis, formal verification, and machine learning.

Title
On the Generalization Mystery in Deep Learning


Dr. Satrajit Chatterjee

Abstract
The generalization mystery in deep learning is the following: Why do over-parameterized neural networks trained with gradient descent (GD) generalize well on real datasets even though they are capable of fitting random datasets of comparable size? Furthermore, from among all solutions that fit the training data, how does GD find one that generalizes well (when such a well-generalizing solution exists)? We argue that the answer to both questions lies in the interaction of the gradients of different examples during training. Intuitively, if the per-example gradients are well-aligned, that is, if they are coherent, then one may expect GD to be (algorithmically) stable, and hence generalize well. We formalize this argument with an easy to compute and interpretable metric for coherence, and show that the metric takes on very different values on real and random datasets for several common vision networks. The theory also explains a number of other phenomena in deep learning, such as why some examples are reliably learned earlier than others, why early stopping works, and why it is possible to learn from noisy labels. Moreover, since the theory provides a causal explanation of how GD finds a well-generalizing solution when one exists, it motivates a class of simple modifications to GD that attenuate memorization and improve generalization. Generalization in deep learning is an extremely broad phenomenon, and therefore, it requires an equally general explanation. We conclude with a survey of alternative lines of attack on this problem, and argue that the proposed approach is the most viable one on this basis.

Paper: https://arxiv.org/abs/2203.10036

Speaker Bio
Sat is an Engineering Leader and Machine Learning Researcher who was at Google AI till recently. His current research focuses on fundamental questions in deep learning (such as understanding why neural networks generalize at all) as well as various applications of ML (ranging from hardware design and verification to quantitative finance). Before Google, he was a Senior Vice President at Two Sigma, a leading quantitative investment manager, where he founded one of the first successful deep learning-based alpha research groups on Wall Street and led a team that built one of the earliest end-to-end FPGA-based trading systems for general purpose ultra-low latency trading. Prior to that, he was a Research Scientist at Intel where he worked on microarchitectural performance analysis and formal verification for on-chip networks. He did his undergraduate studies at IIT Bombay, has a PhD in Computer Science from UC Berkeley, and has published in the top machine learning, design automation, and formal verification conferences.

Past D2T Special Seminar ONLINE

Organizer
東京大学 大学院工学系研究科 附属システムデザイン研究センター アドバンテストD2T寄附講座
東京大学 大学院工学系研究科 附属システムデザイン研究センター 基盤デバイス研究部門
協賛
問い合わせ
肥後昭男
higo"@"if.t.u-tokyo.ac.jp
東京大学 大学院工学系研究科 附属システムデザイン研究センター アドバンテストD2T寄附講座
東京大学 大学院工学系研究科 附属システムデザイン研究センター 基盤デバイス研究部門
Tel: +81-3-5841-0233 FAX: +81-3-5841-1093