VDEC D2T Symposium

December 11th (Fri.), 2009. 10:00-18:00
Takeda-Hall, 5th floor of Takeda Building, The University of Tokyo


Symposium Program (Tentative)

10:00 Opening Remark
10:10 Introduction of VDEC D2T Group
10:20 Invited Talks (1)
Test's Changing Role in the Late-Silicon Era
Tim Cheng (University of California, Santa Barbara)
IFRA: Instruction Footprint Recording and Analysis for Post-Silicon Validation of Robust Systems
Subhasish Mitra (Stanford University)
11:50 Lunch
13:00 Invited Talks (2)
Testing of 3D Integrated Circuits: Challenges and Emerging Solutions
Krishnendu Chakrabarty (Duke University)
Issues and Challenges of Analog Circuit Testing in Mixed-Signal SOC
Haruo Kobayashi (Gunma University)
14:30 Break
15:00 Research Report of VDEC D2T Group
A Characteristic Function Based Method for Identifying a Deterministic Jitter Model in a Total Jitter Distribution
Takahiro Yamaguchi (Advantest Corporation)
Signature-Based Testing for Adaptive Mixed-Signal Systems
Mohamed Abbas (University of Tokyo)
16:00 Break
16:30 Invited Talks (3)
Manufacturing Test of Nanometer Integrated Circuits
Shawn Blanton (Carnegie Mellon University)
On Compositional Observational Equivalence Checking of Hardware
Zurab Khasidashvili (Intel Haifa)
18:00 Banquet

VLSI Design and Education Center (VDEC), The University of Tokyo