VDEC D2T Symposium

June 29th (Tue.), 2010. 10:00-18:30
Takeda-Hall, 5th floor of Takeda Building, The University of Tokyo


Symposium Program (Tentative)

10:00 Opening Remark
10:10 Introduction of VDEC D2T Group
Introduction and Activities of D2T Research Division
Satoshi Komatsu (University of Tokyo)
10:20 Research Activity of VDEC D2T Group
Cost-Effective Test Methodology for Analog and Mixed-Signals in SoCs
Mohamed Abbas (University of Tokyo)
11:05 Invited Talk (1)
Board-Level Fault Diagnosis Methods to Target No-Trouble-Found Failures
Krishnendu Chakrabarty (Duke University)
11:50 Lunch
13:30 Invited Talk (2)
A Tool Chain for Dependable VLSI Design - A challenge to soft-error tolerant VLSI Systems -
Hiroto Yasuura (Kyushu University)
Ultra Dependable VLSI Processor Architecture
Shuichi Sakai (University of Tokyo)
15:00 Break
15:30 Invited Talk (3)
Robust System Design in Scaled CMOS and Beyond
Subhasish Mitra (Stanford University)
Enabling Robust Systems through On-Line Test and Diagnosis
Shawn Blanton (Carnegie Mellon University)
17:00 Break
17:30 Panel Discussion "Dependable VLSI Systems"
Moderator: Masahiro Fujita (University of Tokyo)
Panelists:
Krishnendu Chakrabarty (Duke University)
Subhasish Mitra (Stanford University)
Shawn Blanton (Carnegie Mellon University)
Hiroto Yasuura (Kyushu University)
Shuichi Sakai (University of Tokyo)
Shojiro Asai (Rigaku Corporation)
18:30 Closing

VLSI Design and Education Center (VDEC), The University of Tokyo