The 10th VDEC D2T Symposium
Presentation abstract

Session 1 - Presentation 1

Title: High reliability and process control technique of LSI for Automotive product

Speaker: Takashi Setoya (Toshiba, JEITA)

Abstract: EV、PHVなど、電子化が進む自動車において、 自動車（車載）用半導体の役割は大変重要なものになってきました。 車載に使用される半導体は、高温・高湿など様々な厳しい条件下において、 品質・信頼性への要求が格段に高くなっており、民生用とは異なる設計、製造、 品質管理、スクリーニング技術が必須になります。 本講演では、まず自動車用半導体に要求される品質レベルについて、 初期不良率、耐用寿命、動作温度条件といった要求レベル、 および信頼性試験条件などの観点から民生用半導体との違いを解説し、 高信頼性を達成する具体的手法を、事例などを交えながら、解説します。 Semiconductor devices for automotive applications are getting more important as electronic technologies are involved more in EV, PHV, and others. The required reliability/integrity level for the automotive semiconductors are extremely higher than the ones for the conventional consumer products despite their operational conditions are quite tough in temperature, humidity, and so on. Then, different strategies in design, fabrication, quality assurance, and screening must be indispensable for such semiconductor products. In this talk, the required quality level of the automotive semiconductor products is first discussed from the view points of the early failure rate, constant failure rate period, and operational conditions, along with their test conditions and with the comparison to ordinary consumer products. Then, practical techniques to achieve such high-reliability products are presented with some examples.

Biography: （株）東芝　セミコンダクター＆ストレージ社 品質統括責任者 1983年 東芝入社。 以来個別半導体の品質、信頼性技術開発、バイポーラIC品質信頼性技術、先端プロセス、SOC製品の品質信頼性技術開発に従事。 1985年〜 RCJ故障物理研究委員会委員 1986年〜 日科技連 信頼性研究会、信頼性部会に参加 2005年 大分工場品質保証部長 2010年 品質推進センター長 2013年 品質統括責任者 信頼性学会会員、日科技連 信頼性・品質技術研究会 副委員長 JEITA 実装・製品技術専門委員会 副委員長 JEITA 信頼性小委員会 主査 信頼性学会 会員

Session 1 - Presentation 2

Title: Cross-layer Resilient Design for Automotive Electronics

Speaker: Mehdi Tahoori (Karlsruhe Institute of Technology)

Abstract: Automotive electronics have the stringent safety requirements. However, as the minimum feature size continues to shrink, a host of vulnerabilities influence resiliency of automotive VLSI electronics, such as increased process variation as well as runtime variations due to voltage and temperature fluctuations together with transistor and interconnect aging. This talk will discuss self-awareness, as a new paradigm, for system resiliency in the presence of process and runtime variabilities. The use of data-driven machine-learning is exploited, with the help of various on-chip sensors and monitors, to learn and adapt the best policies for system configuration to achieve resiliency while maintaining other system requirements such as performance, quality of service, power and so on.

Biography: Mehdi Tahoori is professor and Chair of Dependable Nano-Computing (CDNC) at Karlsruhe Institute of Technology (KIT) in Germany since 2009. Before that he was an associate professor of ECE at Northeastern University, Boston, USA. He received his Ph.D. and M.S. in Electrical Engineering from Stanford University in 2003 and 2002, respectively, and B.S. in Computer Engineering from Sharif University, Iran, in 2000. He has published more than 200 conference and journal papers and holds several patents on various aspects of emerging technologies for computing and resilient system design. He is on the organizing and technical program committee of various design automation, test, and reliability conferences and workshops. He is an associate editor of ACM Journal of Emerging Technologies for Computing. He was the recipient of National Science Foundation CAREER Award. He received a number of best paper nominations and awards at various conferences.

Session 2 - Presentation 1

Title: Robust Systems: Overcoming Complexity and Reliability Challenges

Speaker: Subhasish Mitra (Stanford University)

Abstract: Electronic systems are an indispensable part of all our lives. Malfunctions in these systems have consequences ranging from annoying computer crashes, loss of data and services, to financial and productivity losses, or even loss of human life. Robust system design is essential to ensure that future electronic systems perform correctly despite rising complexity and increasing disturbances in the underlying hardware. This talk will address two major goals in the design of robust systems: 1) New approaches to thorough post-silicon validation that scale with tremendous growth in complexity: During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). Traditional pre-silicon verification is inadequate; hence, many critical bugs are detected only after ICs are manufactured. Our new Quick Error Detection (QED) technique overcomes post-silicon validation and debug challenges by detecting bugs a billion times quicker compared to existing approaches, while simultaneously improving bug coverage 4-fold. For an open-source industrial multi-core IC consisting of approximately half-a-billion transistors, QED automatically localizes difficult logic bugs in only a few hours. In contrast, it might take days or weeks (or even months) of manual work (per bug) with existing approaches. 2) Cost-effective tolerance and prediction of failures in hardware during system operation: esilience to hardware failures is a key challenge for a large class of future computing systems that are constrained by the so-called power wall: from embedded systems to supercomputers. To overcome this outstanding challenge, we advocate and examine a cross-layer resilience approach. Two major components of this approach are: (a) System- and software-level effects of circuit-level faults are considered from early stages of system design; and, (b) resilience techniques are implemented across multiple layers of the system stack ? from circuit and architecture levels to runtime and applications ? such that they work together to achieve required degrees of resilience in a highly energy-efficient manner. Illustrative examples to demonstrate key aspects of cross-layer resilience will be discussed.

Biography: Professor Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Before joining Stanford, he was a Principal Engineer at Intel. Prof. Mitra's research interests include robust systems, VLSI design, CAD, validation and test, emerging nanotechnologies, and emerging neuroscience applications. His X-Compact technique for test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems, including numerous Intel products. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. His work on carbon nanotube imperfection-immune digital VLSI, jointly with his students and collaborators, resulted in the demonstration of the first carbon nanotube computer, and it was featured on the cover of NATURE. The NSF presented this work as a Research Highlight to the US Congress, and it also was highlighted as "an important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post, and numerous other organizations worldwide. Prof. Mitra's honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation, "a test of time honor" for an outstanding technical contribution, the Semiconductor Research Corporation's Technical Excellence Award, and the Intel Achievement Award, Intel’s highest corporate honor. He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, Intel Design and Test Technology Conference, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors "for being important to them during their time at Stanford." Prof. Mitra has served on numerous conference committees and journal editorial boards. He served on DARPA's Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.

Session 2 - Presenation 2

Title: Advanced Modeling and Characterization of Bias Temperature Instabilities and Hot Carrier Degradation

Speaker: Tibor Grasser (TU Wien)

Abstract: This talk will cover two interwoven topics, charge trapping as seen for instance in bias temperature instabilities and RTN, as well as creation of interface states due to channel hot carrier stress. Charge trapping in the insulating oxide of MOS transistors will be covered in the first part of the talk. This phenomenon has been linked to a number of detrimental issues, like random telegraph and 1/f noise, bias temperature instabilities, irradiation damage and hot carrier degradation. With the rapid scaling of modern devices these phenomena are becoming more and more important. Although nanoscale devices only contain a small number of defects, each of them can have an increasingly catastrophic impact on the overall device behavior. With the recently developed time-dependent defect spectroscopy (TDDS), the capture and emission of single carriers can be studied. The latest TDDS results will be reviewed together with their implications on modeling and reliability predictions. In particular, a thorough theoretical framework for charge trapping will be discussed, starting from the ab-inito level and reaching up to the device level. In the second part of the talk, channel hot carrier stress in nMOS transistors is discussed, including scaled devices as well as LDMOS transistors. The latest model developments will be summarized, including a discussion of carrier transport for the evaluation of the distribution function which controls the creation of defects. In particular the importance of the various ingredients to the model such as electron-electron scattering will be highlighted.

Biography: Tibor Grasser received his Ph.D. degree in technical sciences from the TU Wien where he is currently employed as an Associate Professor. In 2003 he was appointed director of the Christian Doppler Laboratory for TCAD in Microelectronics. Dr. Grasser is the co-author or author of more than 500 scientific articles, editor of books on advanced device simulation, the bias temperature instability (Springer), and hot carrier degradation (Springer), a distinguished lecturer of the IEEE Electron Devices Society, a senior member of IEEE, has been involved in various functions at outstanding conferences such as IEDM, IRPS, SISPAD, IWCE, ESSDERC, IIRW, and ISDRS, is a recipient of the Best and Outstanding Paper Awards at IRPS (2008, 2010, 2012, and 2014), IPFA (2013), ESREF (2008) and the IEEE EDS Paul Rappaport Award (2011). He was also a chairman of SISPAD 2007 and General Chair of IIRW 2014 and currently serves as an Associate Editor for Microelectronics Reliability (Elsevier).

Session 3 - Presentation 1

Title: Activities of VDEC Advantest D2T Research Division

Speaker: Rimon Ikeno (The University of Tokyo)

Abstract: VDEC Advantest D2T research division was established in VDEC in October 2007. As the name of the research division indicates, it is financially supported by ADVANTEST Corporation. We are currently in its third phase that started in October 2013. The aim of establishment of ADVANTEST D2T research division is to extend research and education environment for VLSI design/test to universities and colleges in Japan. "D2T" means that we consider not only design but also test. Our activities include supplying design/test experts to the industry, advancing research collaboration with the industry, interchanging of researchers with other universities, and providing opportunities for latest research topics through symposia, seminars, and so on. In this talk, such overview of the research division is briefly introduced.

Biography: Rimon Ikeno received his B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo in 1992, 1994, and 1997, respectively. He joined Texas Instruments in 1997, and worked on advanced CMOS devices/process, ultra-low power circuit technology, and low-power DSP core development for mobile applications. After leaving TI in 2008, he worked at two Japanese venture companies for low-power and high-performance computing systems. In 2011, he joined the University of Tokyo again, and currently, he is managing VDEC Advantest D2T research division as a project lecturer. His research interests include advanced device/process technology, VLSI design methodology, DFT, and low-power data processing systems.

Session 3 - Presentation 2

Title: FET-R-C Circuits: A Unified Treatment

Speaker: Tetsuya Iizuka (The University of Tokyo)

Abstract: In today's mixed-signal integrated circuits one will very often find a subcircuit consisting of a loop of a resistor (R), a field-effect transistor (FET) that will be acting as a switch, and a capacitor (C). Depending on the system in which it is embedded, this subcircuit may be acting as a sample-and-hold, as a passive mixer, or as a bandpass filter or bandpass impedance. If employed in an instrument such as an equivalent-time oscilloscope, this circuit would comprise the sampling head. Indeed, this circuit topology has been used for more than 50 years, sometimes employing a diode bridge as the switch, at other times a vacuum tube. It appears in front of almost every analog-to-digital converter, a fundamental building block in today’s digital world. So it comes as a surprise that there exists no comprehensive theory to guide the design of this circuit to a specified frequency response, noise, input impedance, and conversion gain, or that reveals how these quantities might depend on one another and lead to tradeoffs. Although some analyses of this circuit have appeared in the literature, they are either limited in scope or are mathematically complicated, sometimes both. In this presentation, we will present a useful, design-oriented analysis that leads to a simple signal flow graph, which captures the FET-R-C circuit's action completely across a wide range of parameters. This circuit is used commonly in two different ways: as a sample-and-hold, and as a passive mixer. Our analysis allows us, for the first time, to describe the operation of these two circuits in a unified format.

Biography: Tetsuya Iizuka received the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2002, 2004, and 2007, respectively. From 2007 to 2009, he was with THine Electronics Inc., Tokyo, Japan, as a high-speed serial interface circuit engineer. He joined the University of Tokyo again in 2009, and is currently an Associate Professor at VLSI Design and Education Center. He was a Visiting Scholar with University of California, Los Angeles, CA, USA from 2013 to 2015. His research interests include data conversion techniques, high-speed analog integrated circuis, digitally-assisted analog circuits and VLSI computer-aided design. Dr. Iizuka is a member of the Institute of Electrical and Electronics Engineers (IEEE) and the Institute of Electronics, Information and Communication Engineers (IEICE). He is a recipient of the Young Researchers Award from IEICE in 2002, the IEEE ICECS Best Student Paper Award in 2006, and the Yamashita SIG Research Award from Information Processing Society in Japan (IPSJ) in 2007. He is a member of the IEEE ISSCC and CICC Technical Program Committees.

Session 3 - Presentation 3

Title: A Novel Circuit for Transition-Edge Detection

Speaker: Takahiro Yamaguchi (Advantest Laboratories)

Abstract: Traditional binary transition-edge search methods are sensitive to hysteresis, noise and jitter, and also require a relatively large number of samples in order to accurately detect a noisy transition edge. A new transition-edge search circuit is introduced in this paper which utilizes a stochastic comparator group. By incorporating stochastic properties, our proposed circuit design accelerates the accumulation of data and enhances test quality. The background theory underlying this approach is developed and experimentally validated in this paper.

Biography: Takahiro J. Yamaguchi received the B.S. degree in applied physics from Fukui University, Fukui, Japan, in 1976, and the M.S. degree in physics, and Ph.D. degree in electronic engineering from Tohoku University, Sendai, Japan, in 1978, and 1999 respectively. He joined Advantest Corporation in 1978, where he was a Research and Development Project Manager for Fourier analyzers, FFT-based servo analyzers, Michelson-type optical spectrum analyzers, and TV signal analyzers. Since 1991, he has been with Advantest Laboratories Ltd., Miyagi, Japan. Since 2009, he is also a researcher at VDEC, the University Tokyo. Presently he is a visiting professor at Gunma University, Gunma, Japan. Dr. Yamaguchi and his group has presented 14 papers at ITC from year 2000, 8 papers at ISSCC, CICC, RFIC, A-SSCC, ISCAS and 6 journal papers. He was a co-recipient of the DesignCon 2007 Best Paper, and the Honorable Mention Award at ITC2010 for ITC2009 jitter separation paper.