Session 1 - Presentation 1
Title: High reliability and process control technique of LSI for Automotive product | ||
Speaker: Takashi Setoya (Toshiba, JEITA) | ||
Abstract: EV、PHVなど、電子化が進む自動車において、 自動車(車載)用半導体の役割は大変重要なものになってきました。 車載に使用される半導体は、高温・高湿など様々な厳しい条件下において、 品質・信頼性への要求が格段に高くなっており、民生用とは異なる設計、製造、 品質管理、スクリーニング技術が必須になります。 本講演では、まず自動車用半導体に要求される品質レベルについて、 初期不良率、耐用寿命、動作温度条件といった要求レベル、 および信頼性試験条件などの観点から民生用半導体との違いを解説し、 高信頼性を達成する具体的手法を、事例などを交えながら、解説します。 Semiconductor devices for automotive applications are getting more important as electronic technologies are involved more in EV, PHV, and others. The required reliability/integrity level for the automotive semiconductors are extremely higher than the ones for the conventional consumer products despite their operational conditions are quite tough in temperature, humidity, and so on. Then, different strategies in design, fabrication, quality assurance, and screening must be indispensable for such semiconductor products. In this talk, the required quality level of the automotive semiconductor products is first discussed from the view points of the early failure rate, constant failure rate period, and operational conditions, along with their test conditions and with the comparison to ordinary consumer products. Then, practical techniques to achieve such high-reliability products are presented with some examples. | ||
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Session 1 - Presentation 2
Title: Cross-layer Resilient Design for Automotive Electronics | ||
Speaker: Mehdi Tahoori (Karlsruhe Institute of Technology) | ||
Abstract: Automotive electronics have the stringent safety requirements. However, as the minimum feature size continues to shrink, a host of vulnerabilities influence resiliency of automotive VLSI electronics, such as increased process variation as well as runtime variations due to voltage and temperature fluctuations together with transistor and interconnect aging. This talk will discuss self-awareness, as a new paradigm, for system resiliency in the presence of process and runtime variabilities. The use of data-driven machine-learning is exploited, with the help of various on-chip sensors and monitors, to learn and adapt the best policies for system configuration to achieve resiliency while maintaining other system requirements such as performance, quality of service, power and so on. | ||
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Session 2 - Presentation 1
Title: Robust Systems: Overcoming Complexity and Reliability Challenges | ||
Speaker: Subhasish Mitra (Stanford University) | ||
Abstract: Electronic systems are an indispensable part of all our lives. Malfunctions in these systems have consequences ranging from annoying computer crashes, loss of data and services, to financial and productivity losses, or even loss of human life. Robust system design is essential to ensure that future electronic systems perform correctly despite rising complexity and increasing disturbances in the underlying hardware. This talk will address two major goals in the design of robust systems: 1) New approaches to thorough post-silicon validation that scale with tremendous growth in complexity: During post-silicon validation and debug, manufactured integrated circuits (ICs) are tested in actual system environments to detect and fix design flaws (bugs). Traditional pre-silicon verification is inadequate; hence, many critical bugs are detected only after ICs are manufactured. Our new Quick Error Detection (QED) technique overcomes post-silicon validation and debug challenges by detecting bugs a billion times quicker compared to existing approaches, while simultaneously improving bug coverage 4-fold. For an open-source industrial multi-core IC consisting of approximately half-a-billion transistors, QED automatically localizes difficult logic bugs in only a few hours. In contrast, it might take days or weeks (or even months) of manual work (per bug) with existing approaches. 2) Cost-effective tolerance and prediction of failures in hardware during system operation: esilience to hardware failures is a key challenge for a large class of future computing systems that are constrained by the so-called power wall: from embedded systems to supercomputers. To overcome this outstanding challenge, we advocate and examine a cross-layer resilience approach. Two major components of this approach are: (a) System- and software-level effects of circuit-level faults are considered from early stages of system design; and, (b) resilience techniques are implemented across multiple layers of the system stack ? from circuit and architecture levels to runtime and applications ? such that they work together to achieve required degrees of resilience in a highly energy-efficient manner. Illustrative examples to demonstrate key aspects of cross-layer resilience will be discussed. | ||
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Session 2 - Presenation 2
Title: Advanced Modeling and Characterization of Bias Temperature Instabilities and Hot Carrier Degradation | ||
Speaker: Tibor Grasser (TU Wien) | ||
Abstract: This talk will cover two interwoven topics, charge trapping as seen for instance in bias temperature instabilities and RTN, as well as creation of interface states due to channel hot carrier stress. Charge trapping in the insulating oxide of MOS transistors will be covered in the first part of the talk. This phenomenon has been linked to a number of detrimental issues, like random telegraph and 1/f noise, bias temperature instabilities, irradiation damage and hot carrier degradation. With the rapid scaling of modern devices these phenomena are becoming more and more important. Although nanoscale devices only contain a small number of defects, each of them can have an increasingly catastrophic impact on the overall device behavior. With the recently developed time-dependent defect spectroscopy (TDDS), the capture and emission of single carriers can be studied. The latest TDDS results will be reviewed together with their implications on modeling and reliability predictions. In particular, a thorough theoretical framework for charge trapping will be discussed, starting from the ab-inito level and reaching up to the device level. In the second part of the talk, channel hot carrier stress in nMOS transistors is discussed, including scaled devices as well as LDMOS transistors. The latest model developments will be summarized, including a discussion of carrier transport for the evaluation of the distribution function which controls the creation of defects. In particular the importance of the various ingredients to the model such as electron-electron scattering will be highlighted. | ||
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Session 3 - Presentation 1
Title: Activities of VDEC Advantest D2T Research Division | ||
Speaker: Rimon Ikeno (The University of Tokyo) | ||
Abstract: VDEC Advantest D2T research division was established in VDEC in October 2007. As the name of the research division indicates, it is financially supported by ADVANTEST Corporation. We are currently in its third phase that started in October 2013. The aim of establishment of ADVANTEST D2T research division is to extend research and education environment for VLSI design/test to universities and colleges in Japan. "D2T" means that we consider not only design but also test. Our activities include supplying design/test experts to the industry, advancing research collaboration with the industry, interchanging of researchers with other universities, and providing opportunities for latest research topics through symposia, seminars, and so on. In this talk, such overview of the research division is briefly introduced. | ||
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Session 3 - Presentation 2
Title: FET-R-C Circuits: A Unified Treatment | ||
Speaker: Tetsuya Iizuka (The University of Tokyo) | ||
Abstract: In today's mixed-signal integrated circuits one will very often find a subcircuit consisting of a loop of a resistor (R), a field-effect transistor (FET) that will be acting as a switch, and a capacitor (C). Depending on the system in which it is embedded, this subcircuit may be acting as a sample-and-hold, as a passive mixer, or as a bandpass filter or bandpass impedance. If employed in an instrument such as an equivalent-time oscilloscope, this circuit would comprise the sampling head. Indeed, this circuit topology has been used for more than 50 years, sometimes employing a diode bridge as the switch, at other times a vacuum tube. It appears in front of almost every analog-to-digital converter, a fundamental building block in today’s digital world. So it comes as a surprise that there exists no comprehensive theory to guide the design of this circuit to a specified frequency response, noise, input impedance, and conversion gain, or that reveals how these quantities might depend on one another and lead to tradeoffs. Although some analyses of this circuit have appeared in the literature, they are either limited in scope or are mathematically complicated, sometimes both. In this presentation, we will present a useful, design-oriented analysis that leads to a simple signal flow graph, which captures the FET-R-C circuit's action completely across a wide range of parameters. This circuit is used commonly in two different ways: as a sample-and-hold, and as a passive mixer. Our analysis allows us, for the first time, to describe the operation of these two circuits in a unified format. | ||
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Session 3 - Presentation 3
Title:
A Novel Circuit for Transition-Edge Detection
Speaker:
Takahiro Yamaguchi (Advantest Laboratories)
Abstract:
Traditional binary transition-edge search methods are sensitive to hysteresis,
noise and jitter, and also require a relatively large number of samples
in order to accurately detect a noisy transition edge.
A new transition-edge search circuit is introduced in this paper which
utilizes a stochastic comparator group.
By incorporating stochastic properties, our proposed circuit design
accelerates the accumulation of data and enhances test quality.
The background theory underlying this approach is developed and
experimentally validated in this paper.
Biography:
Takahiro J. Yamaguchi received the B.S. degree in applied physics from
Fukui University, Fukui, Japan, in 1976, and the M.S. degree in physics,
and Ph.D. degree in electronic engineering from Tohoku University,
Sendai, Japan, in 1978, and 1999 respectively.
He joined Advantest Corporation in 1978, where he was a Research and
Development Project Manager for Fourier analyzers, FFT-based servo analyzers,
Michelson-type optical spectrum analyzers, and TV signal analyzers.
Since 1991, he has been with Advantest Laboratories Ltd., Miyagi, Japan.
Since 2009, he is also a researcher at VDEC, the University Tokyo.
Presently he is a visiting professor at Gunma University, Gunma, Japan.
Dr. Yamaguchi and his group has presented 14 papers at ITC from year 2000,
8 papers at ISSCC, CICC, RFIC, A-SSCC, ISCAS and 6 journal papers.
He was a co-recipient of the DesignCon 2007 Best Paper, and the Honorable
Mention Award at ITC2010 for ITC2009 jitter separation paper.
Session 3 - Presentation 4
Title:
Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills
Speaker:
Masahiro Ishida (Advantest Corporation)
Abstract:
In this lecture, we present the proposed dynamic power integrity control
method for device testing.
It controls the power supply fluctuations on an ATE in a feed-forward manner
to emulate the actual power supply fluctuation on customers' power supply
environment.
We also demonstrate that our dynamic power integrity control board can
eliminate overkills/underkills due to the difference of power supply
characteristic between an ATE and a practical operating environment of the DUT.
Experimental results of delay fault testing with 105 real silicon devices
show that 95% of overkills/underkills due to the different power supply
characteristics can be eliminated by the proposed method.
Biography:
Masahiro Ishida received the B.S. and the M.S. degree in electronic and
information engineering from Tokyo University of Agriculture and Technology,
Japan, in 1993 and 1995, respectively, and the Ph.D. degree in engineering
from the University of Tokyo, Japan, in 2013.
He joined Advantest Laboratories Ltd. in 1995 and contributed to the
development of jitter measurement method.
From 2009, he worked for Advantest Corporation, Japan and developed
a real-time functional testing method for the multi-level signal
and the digital modulation signal interfaces.
And since 2010, he has been doing a joint research on controlling and testing
the power integrity of the device under test with the University of Tokyo.
His current research interests include testing methods for signal integrity
and power integrity.
Panel discussion
Theme:
Reliability / dependability of industrial standards for automotive systems | ||
Panel Objectives and Description:
In this session,
we would focus on industrial/international standards for
automotive reliability and functional safety such like ISO26262,
AEC-Q100, and others.
Then, we would like to discuss our status of preparations, concerns,
and perspectives from individual panelists' viewpoints.
As the guest panelists, we invite Prof. Tomohiro Yoneda of National Institute of Informatics and Dr. Takao Futagami of TOYO Corporation. They would cover ISO26262 for functional safety of vehicles, and MISRA C for the software standards in it, respectively. | ||
Moderator:
Masahiro Fujita (The University of Tokyo) | ||
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Panelist :
Tomohiro Yoneda (National Institute for Informatics) | ||
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Panelist : Takao Futagami (Toyo Corporation / SESSAME) | ||
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Panelist: Mehdi Tahoori (Karlsruhe Institute of Technology) | ||
Panelist: Subhasish Mitra (Stanford University) |
VLSI Design and Education Center (VDEC), The University of Tokyo