Session 1 - Presentation 1
Title: Design and Test of Micro-Electrode-Dot-Array (MEDA) Digital Microfluidic Biochips | ||
Speaker: Krishnendu Chakrabarty (Duke University & VDEC, The University of Tokyo) | ||
Abstract: A digital microfluidic biochip (DMFB) is an attractive technology platform for automating laboratory procedures in biochemistry. However, today's DMFBs suffer from several limitations: (i) constraints on droplet size and the inability to vary droplet volume in a fine-grained manner; (ii) the lack of integrated sensors for real-time detection; (iii) the need for special fabrication processes and reliability/yield concerns. To overcome the above problems, DMFBs based on a micro-electrode-dot-array (MEDA) architecture, and fabricated using a TSMC 350 nm process, have recently been demonstrated. This presentation will first describe a biochemistry synthesis approach for such MEDA biochips. This synthesis method targets operation scheduling, module placement, routing of droplets of various sizes, and diagonal movement of droplets in a two-dimensional array. Simulation results using benchmarks and experimental results using a fabricated MEDA biochip will be presented to demonstrate the effectiveness of the proposed co-optimization technique. Finally, the presentation will describe an efficient built-in self-test (BIST) solution for MEDA biochips. Simulation results based on HSPICE and experiments using fabricated MEDA biochips will highlight the effectiveness of the proposed BIST architecture. | ||
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Session 1 - Presentation 2
Title: IMPACT: Implantable Microsystems for Personalised Anti-Cancer Therapy | ||
Speaker: Stewart Smith (Edinburgh University & VDEC, The University of Tokyo) | ||
Abstract: IMPACT aims to develop new approaches to cancer treatment using implanted miniaturised, wireless sensor chips the size of a grass seed to monitor the minute-to-minute status of an individual tumour. The project brings together engineers, chemists, veterinary clinicians, social scientists and human cancer specialists from the University of Edinburgh, Heriot-Watt University and the Western General Hospital. This multi-disciplinary group is led by Prof Alan Murray from the University of Edinburgh's School of Engineering. In this presentation, Dr Stewart Smith, will introduce the aims of the IMPACT project and explain the work involved in miniaturising and integrating electrochemical sensors to measure key biomarkers of cancerous tumours. These involve post processing of foundry CMOS electronics and the integration of biosensing materials, as well as the challenges of packaging microelectronic systems for the adverse environment within the human body. | ||
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Session 2 - Presenation 1
Title: Experimental Demonstration of Cancelling Systematic Variation for free-Calibration Stochastic ADC | ||
Speaker: Nguyen Ngoc Mai-Khanh (VDEC, The University of Tokyo) | ||
Abstract: Instead of suppressing process variations, stochastic analog-to-digital converter (ADC) utilizes them to build a multi-Gaussian transfer function based on a number of stochastic comparators. The transfer function or cumulative distribution function (CDF) comprises of all comparator elements' offset distributions and the limited linear region neighboring to the CDF's trip point is used. Two factors, systematic and random variations, contribute to the stochastic ADC's CDF; however, the former should be excluded for the purpose of stochastic ADC operation. In this presentation, we present an experimental demonstration of cancelling systematic variance for free-calibration stochastic ADC. A layout strategy is presented for the purpose of cancelling systematic variation and to obtain Gaussian offset distribution with a reasonable number of comparators. Measurement data of four chips fabricated in a 180-nm CMOS process with a low noise fully differential measurement setup shows an effective LSB resolution smaller 10 times than that of the conventional approach but with the number of comparators less than 10 times. The demonstration on the relationship of number of comparators and the effective resolution LSB of stochastic ADC is helpful for a design-guide for the trade-off between the number of comparator elements, required LSB resolution, die area, and power consumption for fine-resolution stochastic ADC approach. | ||
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Session 2 - Presenation 2
Title: A new method for measuring alias-free aperture jitter in an ADC output | ||
Speaker: Takahiro J. Yamaguchi (Advantest Laboratories Ltd.) | ||
Abstract: This paper proposes a new method for directly measuring alias-free aperture jitter in an ADC output. Both the average ENOB and the worst-case ENOB due to aperture jitter are also measured after the elimination of the aliasing noise. Because it adds only a negligible computation time to an existing ENOB test of a single frequency, it can also be used in an HV production environment and should reduce the overall test time by at least three times. | ||
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Session 2 - Presenation 3
Title: Power Supply Impedance Emulation Technique for ATE Device Power Supply | ||
Speaker: Masahiro Ishida (Advantest Corporation) | ||
Abstract: In this presentation, we proposes a new concept of power supply impedance emulation technique for automatic test equipment (ATE) device power supply that has ability to emulate an arbitrary power supply characteristic. It can emulate power supply impedance of customer environment so as to match the power supply voltage fluctuation waveforms of the ATE and of the customer environment, and hence eliminate overkills and underkills due to power supply characteristic difference between the ATE and a practical operating environment. Our technique adjusts the equivalent impedance by injecting compensation current by a current source attached in parallel with the power supply source. The compensation current is calculated and injected in real-time with a feedback manner based on the power supply voltage measurement with the impedance characteristics of ATE's original power delivery network (PDN) and the customer PDN. | ||
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Session 2 - Presenation 4
Title: High-throughput and high-accuracy electron-beam direct writing | ||
Speaker: Rimon Ikeno (VDEC, The University of Tokyo) | ||
Abstract: The high throughput of character projection (CP) electron-beam (EB) lithography makes it a promising technique for low-to-medium volume device fabrication with regularly arranged layouts, such as for standard-cell logics and memory arrays. However, non-VLSI applications such as MEMS and MOEMS may not be able to fully utilize the benefits of the CP method due to the wide variety of layout figures including curved and oblique edges. In addition, the stepwise shapes that appear because of the EB exposure process often result in intolerable edge roughness, which degrades device performances. In this study, we propose a general EB lithography methodology for such applications utilizing a combination of the CP and variable-shaped beam methods. In the process of layout data conversion with CP character instantiation, several control parameters were optimized to minimize the shot count, improve the edge quality, and enhance the overall device performance. We have demonstrated EB shot reduction and edge-quality improvement with our methodology by using a leading-edge EB exposure tool, ADVANTEST F7000S-VD02, and a high-resolution hydrogen silsesquioxane resist. Atomic force microscope observations were used to analyze the resist edge profiles' quality to determine the influence of the control parameters used in the data conversion process. | ||
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Session 3 - Presentation 1
Title: Options for the integration of technologies with CMOS Integrated Circuits | ||
Speaker: Anthony J. Walton (Edinburgh University) | ||
Abstract: CMOS integrated circuit technology continues to be scaled to smaller geometries as companies follows Moore`s predictions. With this scaling down of dimensions the cost associated with manufacturing ICs at sub 20nm technology has resulted in many companies being either unable, or unwilling, to justify such an investment. As a consequence many have decided to go fabless while others have diversified into new device types and more niche application areas. One very attractive option for both IC producers and fabless companies to use a standard silicon as a platform for system integration. The added value associated with post-processing directly on top of the silicon circuitry can then be provided in-house by companies with the required technology or via third party providers for fabless operations. This presentation examines many of the issues associated with integrating foundry and custom IC wafers with both new materials and technologies such as MEMS based sensors and actuators. It discusses the options available for companies considering such applications and presents examples of successful implementations of a number of different approaches. | ||
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Session 3 - Presentation 2
Title: 3D Integrated CMOS-Memristor Hybrid Circuits: Devices, Integration, Architecture, and Applications | ||
Speaker: Kwang-Ting (Tim) Cheng (Hong Kong University of Science and Technology) | ||
Abstract: I will give an overview of our recent research efforts on monolithic 3D integration of CMOS and memristive nanodevices. These hybrid circuits combine a CMOS subsystem with multiple layers of nanowire crossbars, consisting of arrays of two-terminal memristors, all connected by an area-distributed interface between the CMOS subsystem and the crossbars. Combining the advantages of CMOS technology with the extremely high density of memristors and interface vias, this approach could offer unprecedented memory density and bandwidth at manageable power dissipation, and enable new memory-centric computing paradigms. Specifically, I will highlight our results in four areas: (1) memristive device development and engineering which achieves better performance, endurance and uniformity, (2) 3D monolithic integration of CMOS with up to 8 layers of memristive crossbars, (3) architectures for building low-power, reliable resistive RAM (ReRAM), and (4) applications to bio-inspired mixed-signal computing. | ||
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Panel discussion
Theme: Breakthrough technology and application of heterogeneous micro/nano systems for industrial/economic success | ||
Moderator:
Hiroyuki Fujita (Institute of Industrial Science, The University of Tokyo) | ||
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Panelists: | ||
Anthony Walton (Edinburgh University)
Tim Cheng (Hong Kong University of Science and Technology) Krishnendu Chakrabarty (Duke University & VDEC, The University of Tokyo) Stewart Smith (Edinburgh University & VDEC, The University of Tokyo) |
VLSI Design and Education Center (VDEC), The University of Tokyo