VDEC D2T Symposium

March 9th (Wed.), 2011. 10:00-18:00
Takeda-Hall, 5th floor of Takeda Building, The University of Tokyo


Automated Debugging - Between Localization and Explanation of Bugs
Goerschwin Fey (Bremen University)
Design verification is supported by powerful tools that detect the existence of bugs in a design. But the following debugging step to identify and remove the bug is a time consuming task that is mainly done manually. Tool automation for debugging has been developed recently. One class of tools localizes potential fault locations to speed up the debugging task. The other class of tools explains the reasons for errors being observed. This talk briefly considers both approaches and highlights commonalities as well as differences.

High-speed clocked comparator for on-chip signal monitoring applications
Mohamed Abbas (Assiut University/University of Tokyo)
Takahiro Yamaguchi (Advantest Laboratories)
In this talk, I will present a design for an on-chip high-speed clocked-comparator for high frequency signal digitization. The comparator consists of two stages, amplification and regenerative, comprising a total of 10 MOS transistors. The design is implemented in 65nm CMOS technology. In addition, I will introduce a cost effective technique for measuring the maximum speed of the clocked comparator. The measurement and simulation results show that the proposed design has an average of 31% higher speed and 17% less active area than the conventional design.

3D Imaging and Analysis System Using Terahertz Waves
Eiji Kato, Motoki Imamura (Advantest Corporation)
We have developed the g3D Imaging and Analysis Systemhthat uses terahertz waves, the world's first   such system for practical applications. This system has an unprecedented capability for nondestructive three-dimensional spectroscopic analysis of the spatial distribution of constituents.

3D Power Ground Network Analysis
Chung-Kuan Cheng (University of California, San Diego)
We discuss the power ground network structure and electrical behavior of 3D ICs with through silicon vias. We will describe the circuit modeling, the excitation patterns following power laws and the worst case stimuli. We explain the antiresonant frequencies and rogue wave phenomenon due to 3D structures. The tools and methodologies to analyze the power integrity will be presented.

Post-Silicon Validation of Robust Systems
Subhasish Mitra (Stanford University)
Malfunctions in electronic systems have enormous consequences as systems become more complex, interconnected, and pervasive. Robust
system design is required to ensure that future electronic systems perform correctly despite rising levels of complexity and increasing disturbances. Hardware failures are especially a growing concern because existing test and validation methods barely cope with todayfs complexity. Moreover, at remarkably small geometries, several failure mechanisms, largely benign in the past, are becoming important. This talk will focus on two recent post-silicon validation techniques for robust systems: IFRA and QED.
IFRA, an acronym for Instruction Footprint Recording and Analysis, overcomes major challenges associated with an expensive step in post-silicon validation of processors - pinpointing the bug location and the instruction sequence that exposes the bug from a system failure such as a crash. IFRA does not require full system-level reproduction of bugs or full system-level simulation. Simulation results on complex super-scalar processors (Intel Nehalem architecture, Alpha 21264) demonstrate IFRA's effectiveness in accurately localizing electrical bugs with very little impact on overall chip area.
Post-silicon bug localization challenges are exacerbated by long error detection latencies. QED, an acronym for Quick Error Detection, overcomes this challenge by automatically transforming existing post-silicon validation tests into new validation tests with significantly reduced error detection latencies. Results obtained from hardware experiments on quad-core IntelR Core? i7 hardware platforms and from simulations demonstrate that QED significantly improves (i.e., reduces) error detection latencies by six orders of magnitude. Moreover, QED tests improvecoverage by detecting errors that escape original non-QED tests.

Coverage Metrics for Post-Silicon Validation
Kwang-Ting(Tim) Cheng (University of California, Santa Barbara)
Both functional bugs and electrical bugs are growing concerns, due to increasing design complexity, shrinking noise margins and increasing variability. However, it has become nearly impossible to accurately model, detect, and fix all these bugs in pre-silicon verification. Therefore they must be specifically targeted and thoroughly tested in post-silicon validation.
Currently there is no suitable coverage metric available for evaluating the quality of validation tests and the effectiveness of DfD (design-for-debug) structures for post-silicon validation. In this talk, we will first discuss the criteria of a good coverage metric for post-silicon validation: it must be efficiently computable for system-level models and tests, must be low-level aware to allow targeting of electrical bugs, and must account for the limited observability in silicon.
We will then discuss the development of coverage metrics which are designed to meet these challenges. Specially, we introduce our recent study in which the target coverage points are a set of fault-symbols, either generated from suspect expressions in a system model (for targeting functional bugs), or extracted from low-level simulation traces (for targeting electrical bugs). We will further discuss a mutation-based bug injection tool for C/C++/SystemC models which facilitates further development of validation coverage metrics and automated diagnosis. We will show experimental results comparing the proposed coverage measures with the existing coverage measures used either for pre-silicon verification or manufacturing testing.

VLSI Design and Education Center (VDEC), The University of Tokyo