The 7th VDEC D2T Symposium

December 11th (Tue), 2012. 10:00-18:00
Takeda-Hall, 5th floor of Takeda Building, The University of Tokyo


Test Time Reduction By Exploring Spatial and Test-Item Correlations Using Statistical Regression Techniques
Kwang-Ting (Tim) Cheng (University California, Santa Barbara)
The virtual probe (VP) technique, based on recent breakthroughs in compressed sensing, has demonstrated its ability for accurate prediction of spatial variations from a small set of measurement data. In the first part of this talk, we explore VP's application to production test time reduction (TTR). For a number of test items, the measurement data from a small subset of chips can be used to accurately predict the performance of other chips on the same wafer without explicit measurement. Depending on the extracted statistical characteristics, test items can be classified into three categories: highly predictable, predictable, and un-predictable. A case study of an industrial RF radio transceiver with 51 production test items shows that a good fraction of these test items (39 out of 51 items) are predictable or highly predictable. Thus applying this technique can on average replace ~60% of test measurement by prediction.
In the second part of the talk, we further describe a complementary TTR methodology based on a statistical regression technique called LASSO (Least Absolute Shrinkage and Selection operator). Our method builds an inter-test-item correlation model among all test items, based on which some of the test items can be identified for elimination from measurement and thus resulting in test time reduction. We demonstrate its successful application for minimizing the number of parametric test items for an industrial power-monitoring chip.

Power Integrity Control of ATE for Emulating Customer's Power Supply Characteristic
Masahiro Ishida (Advantest)
In this lecture, we propose a power integrity control technique for device testing. The proposed method controls the power supply fluctuations on an ATE in a feed-forward manner by supplying a compensation current into the power supply line. It enables a DUTs' power supply fluctuation on an ATE to emulate the actual power supply fluctuation on customers' power supply environment.

New Capability Enables System Level Functional Test and Automated Test Program Generation on ATE
Satoru Kitagawa (Advantest)
This presentation introduces a new capability on ATE, called "Functional Test Abstraction (FTA)", which enables to execute system level functional test of complex SoC including high speed interface. FTA also enables automated test program generation from Design Verification Environment (DVE).

Portable/Desktop Testing Solution for engineering with Cloud
Manabu Kimura (Cloud Testing Service)

Nanoscale circuit structures for measurement and test
Jacob A. Abraham (University of Texas at Austin)
Advances in integrated circuits are enabling accurate and low-cost measurement of on- and off-chip electrical parameters. However, while technology scaling increases integrated circuit speeds, the lower voltages and increasing parameter variations are making it difficult to implement traditional analog circuits. This talk will explore digital-like circuit structures for measurement and test which will scale well in nanoscale dimensions and which consume very little power. Applications of such circuits will be discussed, including measurement of small delays, data conversion and accurate frequency detection.

Time-Mode Signal Processing and Its Impact On Analog/Mixed-Signal/RF Testing
Gordon Roberts (McGill University)
The gap between analog and digital circuit design has been steadily increasingly over the past four decades of semiconductor development, largely driven by advances in digital CAD. Today the situation is considered critical. Using a simple design productivity metric like the number of transistor utilized per man-months for any given design, the analog team can incorporate anywhere between 10 - 100 transistors per man-months whereas the digital design team can utilize 100's of thousands or more per man-months. It is the objective of this talk to look at how time-mode signal processing can be used to reduce the analog-digital design gap and, more specifically, to address the analog/mixed-signal/RF test question. The talk will begin with a look at some of the early developments of time-mode techniques for electron emission measurements in nuclear science experiments to present-day methods used for onchip DFT/BIST purposes. Experimental data suggests that time-mode circuits have the ability to operate at much higher speeds that their voltage mode counterparts, although resolution and noise issues have yet to be brought under design control. Time-mode signal processing is largely based on the control of the delay of a single digital inverter. As such, time-mode circuits generally follow a digital design methodology (synthesizable) and can be structurally tested using digital scan. This talk will conclude with a call for change, largely in the analog design community, to help reduce the analog-digital design gap.

Testing & Debugging On-Chip Jitter without a Reference Clock or High-Frequency Pins
Takahiro Yamaguchi (Advantest Laboratories)
This presentation reviews the theory and introduces the architecture for a clock source with low phase noise and for measuring timing jitter. This approach utilizes a sample mean and sum of two random variables, and can be implemented in CMOS or SiGe BiCMOS circuits.

A CMOS Flash TDC with 0.84-1.3 ps Resolution Using Standard Cells
James Tandon (University of Tokyo)
This talk presents a deterministic flash time-to-digital converter architecture that can be implemented using cross-coupled NAND standard cells with variable transistor widths. An input pulse slope control circuit, which demonstrates tuning of the TDC dynamic range is also presented. Both simulation and experiment were used to verify this architecture in a 65 nanometer process. The TDC has a tunable resolution from 0.84ps to 1.3ps using the slope control circuit.

Panel Discussion "Post-Silicon Validation and Test in Huge Variance Era"
Panel Organizer: Takahiro J. Yamaguchi
Kwang-Ting (Tim) Cheng (University California, Santa Barbara)
Jacob A. Abraham (University of Texas at Austin)
Gordon W. Roberts (McGill University)
Moderator: Takahiro J. Yamaguchi
Panel Objectives and Description:
At the ITC 1999, Pat Gelsinger from Intel delivered an important keynote address where he outlined the need for a low-pin count tester with lower performance pin electronics to meet the stringent test cost requirements of a billion transistor machine. At the ITC 2009, engineers from AMD came forward with an I/O test solution that is believed to meet the Intel challenge using a cash-resident self-testing strategy combined with an external low-pin count tester.
How can we drive major challenges to post-silicon validation and in huge variance era?  Technology scaling enables us to trade off amplitude resolution for time resolution.  Accordingly, both internal and external tests, some of which use low-pin count testers, are also shifting from voltage centric tests to timing centric tests.  How can time resolution be used to push the timing centric tests beyond current limitations?  How can spatial resolution be realized to enhance yields in terms of both die-to-die variations and within-die variations?  What is necessary to provide robust on-chip solutions subject to huge variations, which may be combined with an external low-pin count tester?

VLSI Design and Education Center (VDEC), The University of Tokyo