Abstracts
| 3D TSV Test: Myths, Challenges, and Solutions |
| Erik H. Volkerink (Verigy US Inc. _ Advantest Group) |
| The 3D TSV revolution is happening! After a slow start, the solution for increased circuit density, lower power consumption and improved bandwidth appears to be on its way for adoption in the industry. While a lot of test challenges have been addressed with innovative solutions, there still remain many to be tackled to fully adopt 3D TSVs. This paper provides an overview of the state-of-the-art in 3D TSV test, presents the major test challenges as well as the myths and misconceptions, and introduces new test solutions and concepts. |
| Application of a Continuous-Time Level Crossing Quantization Method for Timing Noise Measurements |
| Takahiro Yamaguchi (Advantest Laboratories) |
| This paper introduces a new Level-Crossing ADC (LCADC) architecture which employs the novel use of a clocked comparator. The proposed LCADC can measure a timing noise spectrum with wide dynamic range and wide frequency range. An extension of the underlying theory of the performance measurement of an LCADC is also included. |
| Electron beam lithography: history, issues, and challenges |
| Masaki Yamabe (Fujitsu Semiconductor Ltd.) |
| Electron beam (e-beam) lithography, especially e-beam direct write (EBDW) lithography, has a history of over 50 years. This history is as long as that of integrated circuits. The advantages of e-beam lithography are its high resolution capability and pattern generation capability. In semiconductor manufacturing, the pattern generation capability is utilized in mask writing and in direct writing applications. The key issue of e-beam lithography has been and still is its throughput. The challenges and evolution of e-beam tool are always for the improvement of throughput. In the talk, brief history of e-beam lithography, its issues and the reasons, and challenges to overcome the low-throughput issue, will be presented. |
| EB Direct Writing Technology for Device Production with Character Projection Function |
| Takashi Maruyama (e-Shuttle Inc.) |
| We have established CP (character projection) based EBDW technology for 65nm device production including MPW (multi products wafer) prototyping business in our company. As for future 14nm node high volume manufacturing, photo based lithography has been reaching its resolution limit, and multi beam EBDW methodology MCC (multi column cell) combined with this CP function is one of the most promising technologies. Although in addition to multi-beam parallel exposure, drastic exposure shot count reduction is indispensable to attain throughput of 100 WPH which meets high volume manufacturing requirement. All device circuit blocks should be structured with only CP defined parts and we should trace back to upstream design flow to RTL. And so we need joint development with VEDC which has expertise of LSI design. I would like to introduce past our technical outputs and research motivation in VDEC to attain our future target. |
| Nanotechnet club: Ultra-short turn-around-time MEMS Research by EB Direct Writing Environment in Takeda Cleanroom |
| Yoshio Mita (University of Tokyo) |
| High-speed digital I/O characterization with ATE: is there a future? |
| Jose-Antonio Moreira (Verigy, Advantest Group) |
| Digital I/O interfaces with multi-gigabit data-rates are now commonly incorporated into low cost consumer applications. Standards such as PCI-Express have been driving the data rates to higher levels with each generation. Thorough characterization of these I/O cells is a critical component for developing a low-cost testing strategy in high volume production. This leads to the question of whether traditional ATE can still provide a viable solution at these data rates, or if bench instrumentation is the only option? In this presentation we will describe the challenges faced by an ATE based solution, and illustrate that the decision is not a simple choice between ATE and bench instrumentation, but rather how to take advantage of both approaches to create a single strategy that leverages the strengths of each. |
| Real-Time Testing Method for High-Speed Multi-Level Signal Interface |
| Masahiro Ishida (Advantest) |
| In this lecture, we propose a real-time testing method for multi-level signal interface. It utilizes multi-level drivers that can modulate output voltage and multi-level comparators based on a dynamic threshold concept. Experimental results are discussed with a prototype circuit that demonstrates the proposed concept applied to a 16-Gbps 4-PAM test system. Applications of the proposed method are also discussed. |
VLSI Design and Education Center (VDEC), The University of Tokyo