Services Provided by VDEC


LSI Chip Fabrication

Various VLSI fabrication services are provided to all VDEC users. Presently up to 6 different technologies are available to users in Japan for academic or educational usage. We have no plan to provide chip fabrication service to request from outside Japan yet. The technologies below have 1-6 runs a year. The fabrication period is about 3 months.

Foundry Feature Layer Die Size Package
On Semicoductor Japan CMOS 1.2um 2-Poly, 2-Metal 2.3mm x 2.3mm
4.8mm x 4.8mm
7.3mm x 7.3mm
QFP80
QFP160
QFP208
Rohm Co., Ltd. CMOS 0.35um 2-Poly, 3-Metal 2.4mm x 2.4mm
4.9mm x 4.9mm
9.8mm x 9.8mm

QFP80
QFP160
QFP208

Hitachi CMOS 0.18um 1-Poly, 5-Metal 2.8mm x 2.8mm
5.9mm x 5.9mm
PGA257, QFP160
NEC Compound Semiconductor Devices Ltd. Bipolar 0.8um 3-Metal 2.0mm x 2.0mm
QFP80
OKI Co. Ltd. CMOS SOI 0.15um 1-Poly, 5-Metal 2.5mm x 2.5mm
5.0mm x 5.0mm
QFP80
ASPLA CMOS 90nm 1-Poly, 6-Metal

2.5mm x 2.5mm
2.5mm x 5.0mm
5.0mm x 5.0mm

QFP80
QFP208

Figure 1 VDEC users (a) In terms of universities (b) In terms of professors

Figure 1 shows the changes of the number of VDEC users from 1994 to 2004. In 2004, there were totally 648 professors in 153 universities and colleges participating chip design and fabrication in VDEC.

Figure 2 (a) Number of fabricated chips (b) Silicon area of fabricated chips


In 2004, both the number and the silicon area of fabricated chips in VDEC keeps almost the same as 2003. It is shown in Fig. 2 that 404 chips in about 5960 square-mm silicon area have been designed and fabricated in last year.

Figure 2 (c) Number of published papers related to chips fabricated at VDEC

Over 680 papers or technical reports, which are related to chips fabricated at VDEC, were published in 2004. Fig. 2(c) shows that in 2004, there is a great increase of published papers compared with 2003.

Test and Mesurement Support

The fabricated chips will be split and packaged into plastic or ceramic packages according to users' request. After chip identifications at VDEC, chips are sent back to users for measurement and evaluation. For chip evaluation, VDEC can provide the high speed logic tester. On the other hand, EB (electronic beam) prober and FIB (Focused Ion Beam) facility are also available for locating and even modifying the design fault of the fabricated chip. Chip sockets and connection boards for most of VDEC chip packages are also provided to users who will measure chips with their own method.

Electron beam writer system for mask fabrication is a new service provided by VDEC since 2004.

CAD Software Tools Support

Figure 3 Usage of CAD software (a) Issued CAD licenses (b) Number of CAD users

Mainstream CAD software from Cadence, Synopsys, Mentor Graphics and Magma etc., are utilized and supported. VDEC makes contracts with the CAD vendors and provides 500 to 2000 CAD licenses for each CAD tool to end-users in Japan. Figure 3 depicts issued software licenses and lab users that utilized the CAD tools. In 2004, totally over 8500 CAD software licenses were issued to 281 lab users.

VDEC will continue its support on LSI design education and chip fabrication. More technologies with well-developed libraries will be introduced. It is believed that VDEC users can get further choices and services in the near future.

LSI Design Education

To assist VDEC users with mastering up-to-date LSI design knowledge and techiniques, CAD training courses oriented to VDEC users are arranged twice a year by VDEC and CAD vendors such as Cadence, Synopsys and Avant!. Each 3-5 days course including training and lab exercise is provided to over 40 students or researchers free of charge.

On the other hand, an education course oriented to company designers is also held once a year. Various kinds of introduction on LSI design, from basic HDL design technology to advanced design examples, are given to 50-100 people at this "refresh course".