VDEC D2T Symposium 2011

March 9th (Wed.), 2011. 10:00-18:00
Takeda-Hall, 5th floor of Takeda Building, The University of Tokyo


Symposium Program

10:00 Opening
10:30 Introduction of VDEC D2T Group
Introduction and Activities of D2T Research Division
Satoshi Komatsu (University of Tokyo)
10:50 Invited Talk (1)
Automated Debugging - Between Localization and Explanation of Bugs
Goerschwin Fey (Bremen University)
11:30 Research Activity of VDEC D2T Group
High-speed clocked comparator for on-chip signal monitoring applications
Mohamed Abbas (Assiut University/University of Tokyo)
Takahiro Yamaguchi (Advantest Laboratories)
12:10 Lunch
13:30 Special Invited Talk
3D Imaging and Analysis System Using Terahertz Waves
Eiji Kato, Motoki Imamura (Advantest Corporation)
14:10 Invited Talk (2)
3D Power Ground Network Analysis
Chung-Kuan Cheng (University of California, San Diego)
14:50 Break
15:20 Invited Talk (3)
Post-Silicon Validation of Robust Systems
Subhasish Mitra (Stanford University)
Coverage Metrics for Post-Silicon Validation
Kwang-Ting(Tim) Cheng (University of California, Santa Barbara)
16:40 Break
17:00 Panel Discussion
"Testing future VLSI systems: short-, mid-, and long-term challenges and solutions"
Moderator: Kwang-Ting(Tim) Cheng (University of California, Santa@Barbara)
Panelists:
Chung-Kuan Cheng (University of California, San Diego)
Subhasish Mitra (Stanford University)
Goerschwin Fey (Bremen University)
Takahiro Yamaguchi (Advantest Laboratories)
18:00 Closing
18:10 Banquet

VLSI Design and Education Center (VDEC), The University of Tokyo