| 10:00 |
Opening |
| 10:10 |
Session 1 |
|
Test Time Reduction By Exploring Spatial and Test-Item Correlations Using
Statistical Regression Techniques
Kwang-Ting (Tim) Cheng (University California, Santa Barbara) |
|
Power Integrity Control of ATE for Emulating Customer's Power Supply Characteristic
Masahiro Ishida (Advantest) |
|
New Capability Enables System Level Functional Test and Automated Test
Program Generation on ATE
Satoru Kitagawa (Advantest) |
| |
Portable/Desktop Testing Solution for engineering with Cloud
Manabu Kimura (Cloud Testing Service) |
| 12:00 |
Lunch |
| 13:20 |
Session 2 |
|
Nanoscale circuit structures for measurement and test
Jacob A. Abraham (University of Texas at Austin) |
|
Time-Mode Signal Processing and Its Impact On Analog/Mixed-Signal/RF Testing
Gordon Roberts (McGill University) |
| 15:00 |
Break |
| 15:30 |
Session 3 |
|
Testing & Debugging On-Chip Jitter without a
Reference Clock or High-Frequency Pins
Takahiro Yamaguchi (Advantest Laboratories) |
|
A CMOS Flash TDC with 0.84-1.3 ps Resolution Using Standard Cells
James Tandon (University of Tokyo) |
| 16:30 |
Panel Discussion "Post-Silicon Validation and Test in Huge Variance Era" |
| 17:50 |
Closing |
| 17:00 |
Reception |