The 14th VDEC D2T Symposium, The University of Tokyo

September 6th (Fri.), 2019
Takeda Hall, 5th floor of Takeda Building, The University of Tokyo

(日本語版, Japanese page)


News:

- Symposium homepage was opened. (2019/7/12)
- Symposium homepage was updated. (2019/7/16)
- Registration started. (2019/7/22)
- Symposium homepage was updated. (2019/7/25)
- Abstract was updated. (2019/8/5)


Symposium Overview

Organizer VLSI Design and Education Center (VDEC), The University of Tokyo
Sponsor ADVANTEST Corporation
Supporters (provisional) The Institute of Electronics, Information and Communication Engineers (IEICE)
Information Processing Society of japan (IPSJ)
IEEE SSCS Japan Chapter
IEEE SSCS Kansai Chapter
The Study Group of the integrated MEMS, JSAP
The Institute of NANO Testing (INANOT)
Japan Electronics and Information Technology Industries Association (JEITA)
Semiconducto Equipment Association in Japan (SEAJ)
SEMI Japan
Power Device Enabling Association (PDEA)
KEISOKU ENGINEERING SYSTEMS (KESCO)
Admission fee Not required
Presentation Language English

From the organizer:

"D2T Symposium" will be held on 6th September, 2019, as 14th meeting of symposium series first started in 2008. We have been pursuing in "design", "test", and their bridging technologies in the symposia as indicated in the name "D2T" that means "Design to Test".
This year, we will invite lecturers overseas, Professor Degang Chen, Dr. Alan Alan Mishchenko, Professor Priyank Kalla, Professor Adit Singh from US, Professor K.-T. Tim Cheng from Hong Kong, Professor Tsung-Hsien Lin from Taiwan, and Assoc. Professor Gilgueng Hwang from France for their distinguished research topics.
We look forward to all of your participation in the symposium.

This symposium is follwing days of The 3rd International Test Conference in Asia 2019 (ITC-Asia) (Sep. 3-5) at Tokyo Denki Univesity, Kita-Senju, Tokyo. Please also attend the conference. The 3rd ITC-Asia 2019


Symposium Abstract (日本語版, Japanese version)

10:00 Opening remarks
10:15 Session 1 - Special Lecture I
"Circuit-Based Intrinsic Methods to Detect Overfitting"
Alan Mishchenko (University of California, Berkeley)
Abstract
The focus of this paper is on intrinsic methods to detect overfitting. These rely only on the model and the training data, as opposed to traditional extrinsic methods that rely on performance on a test set or on bounds from model complexity. We propose a family of intrinsic methods called Counterfactual Simulation (CFS) which analyze the flow of training examples through the model by identifying and perturbing rare patterns. By applying CFS to logic circuits we get a method that has no hyper-parameters and works uniformly across different types of models such as neural networks, random forests and lookup tables. Experimentally, CFS can separate models with different levels of overfit using only their logic circuit representations without any access to the high level structure. By comparing lookup tables, neural networks, and random forests using CFS, we get insight into why neural networks generalize.
"Effective and practical AMS DfT techniques for achieving robust performance and life-time reliability"
Degang Chen ( Iowa State University)
Abstract
In the coming 5G and IoT age, reliability and functional safety of mission-critical applications impose stringent self-diagnosis and self-healing capability requirements on electronic circuits and systems. In this talk, we will describe effective and practical techniques enabling in-field self-test and self-calibration of analog to digital converters. In particular, we will describe techniques to reduce test data acquisition time by >100X, to relax test-instrument requirements by >100X without affecting test accuracy, and to implement the ADC self-test and self-calibration scheme in an automotive microcontroller.
"Sensor Readout Circuits for IoT/Bio-Medical Applications"
Tsung-Hsien Lin (National Taiwan University)
Abstract
Sensors are playing increasingly important roles in applications such as IoT, wearable devices, bio-medical electronics. The sensor readout circuit must be able to extract weak sensor signal under noisy environment. The flicker noise and offset voltage of the readout circuit should be mitigated with proper techniques. Furthermore, low-power consumption is mandated to prolong the device lifetime. In this talk, several works address the aforementioned issues will be presented. VCO-based architecture that combines the analog front-end with ADC will also be introduced.
12:30 Lunch break
14:00 Session 2 - Special Lecture II
"Design, Fabrication and Characterizations of On-chip Micro/nanorobotic Swimmers Toward Biological Applications"
Gilgueng Hwang (Centre for Nanoscience and Nanotechnology, University Paris-Saclay, France)
Abstract
Untethered micro/nanorobotic swimmers are promising tool towards biologic or biomedical applications thanks to their highly accessible feature to tiny capillaries. However great challenges in design, fabrication and low Reynolds number physics have limited such applications. We integrated multidisciplinary technologies of micro/nanofabrication, microfluidics and microrobotics to those challenges. We recently developed highly energy efficient and fully controllable on-chip magnetic micro/nanorobotic swimmers with remote controlled functions such as cargo transport and sensing. This talk is divided in two parts. First, I will introduce our recently developed micro/nanorobotic swimmers which can serve as mobile micromanipulator or physical sensor inside microfluidic channels. The second part will be devoted to introduce physical property characterizations such swimmers by micromanipulation with scanning electron microscope or atomic force microscope.
"On Rectification of Arithmetic Circuits with Algebraic Geometry"
Priyank Kalla (The University of Utah)
Abstract
Formal verification of arithmetic circuits checks whether or not a gate-level circuit correctly implements a given specification model. In cases where this equivalence check fails -- i.e. the presence of a bug is detected -- it is required to: i) debug the circuit, ii) identify a set of nets (signals) where the circuit might be rectified, and iii) compute the corresponding rectification functions at those locations. Contemporary techniques make use of QBF-solvers, Craig-interpolation and Boolean SAT to solve this problem. While these have shown promise with control-dominated applications, these techniques are infeasible to debug and rectify arithmetic datapaths and circuits.

In this talk, I will describe post-verification debug and rectification of arithmetic circuits using computational algebraic geometry based approaches. By modeling the circuits using polynomials over appropriate fields, I will show how the rectification problem can be formulated using the Nullstellensatz, and solved using Groebner Basis (GB) algorithms. As GB-algorithms exhibit high computational complexity, I will further describe techniques that exploit the topology of the circuit-under-test to efficiently solve the problem for large datapath circuits. I will demonstrate the efficacy of the approach with experimental results, and conclude the talk with a perspective on application of these approaches to logic synthesis of approximate circuits.
15:30 Break
16:00 Sesson 3 - Special Lecture III
"Electronic-Photonic Design Automation"
K.-T. Tim Cheng (Hong Kong University of Science and Technology)
Abstract
Nanophotonic interconnects have demonstrated promising bandwidth capacity in datacom regime. Greater integration of silicon photonics calls for support from design automation methodologies that applies across device, circuit, and system levels. In this talk, I will introduce our effort on variation-aware compact modeling of silicon photonics devices and electronic-photonic co-simulation. Based on validated models, system-level optimization techniques were also investigated to perform variation management and enhance the energy efficiency of optical interconnects at large scale.
"The Next Major Test Challenge: Low Power Designs"
Adit Singh (Auburn University)
Abstract
For the past two decades, innovations in test methodologies have been significantly driven by the stringent reliability requirements of the automotive industry, most recently from the push towards computer assisted and autonomous driving systems. In this presentation we look beyond this focus of current industrial research to identify the next big challenge in test: battery constrained designs being operated at increasingly lower voltages to minimize energy consumption. In the absence of an effective low cost scan structural test methodology for such designs, parts such as smart phone and notebook processor SOCs are relying on “brute-force” functional system level tests. We discuss why current scan based tests are not sufficiently effective at detecting failing parts for such designs, and explain the significant challenges structural tests face in overcoming this limitation.
17:30 Session 4 - VDEC D2T Research Division
"Activities of D2T research division"
Akio Higo (VDEC D2T, The University of Tokyo)
17:55 Closing
18:00 Reception


Registration (free of charge)

On site registration is available.
Please register HERE.


Access to the Symposium

Please look at the MAP.


D2T Symposium history

Past D2T Symposium pages


Contact

ADVANTEST D2T Research Divison,
VLSI Design and Education Center (VDEC), The University of Tokyo
Room 404, Takeda Building, Yayoi 2-11-16, Bunkyo-ku, Tokyo, 113-0032, Japan
Tel: +81-3-5841-0233 FAX: +81-3-5841-1093
E-mail: higo[at]if.t.u-tokyo.ac.jp


VLSI Design and Education Center (VDEC), The University of Tokyo