The 17th D2T Symposium, The University of Tokyo

Organizer	Systems Design Lab (d.lab), School of Engineering, The University of Tokyo
Sponsor	ADVANTEST Corporation
Supporters	The Institute of Electronics, Information and Communication Engineers (IEICE) Information Processing Society of japan (IPSJ) IEEE SSCS Japan Chapter IEEE SSCS Kansai Chapter The Study Group of the integrated MEMS, JSAP The Institute of NANO Testing (INANOT) Japan Electronics and Information Technology Industries Association (JEITA) Semiconducto Equipment Association in Japan (SEAJ) SEMI Japan Power Device Enabling Association (PDEA) KEISOKU ENGINEERING SYSTEMS (KESCO)
Admission fee	Not required
Presentation Language	English

From the organizer:

"D2T Symposium" will be held on 15th September, 2022, as 17th meeting of symposium series first started in 2008.We have been pursuing in "design", "test", and their bridging technologies in the symposia as indicated in the name "D2T" that means "Design to Test".

This year, we will invite lecturers overseas, Assistant Professor, Zhongrui Wang from Hong Kong University, Reika Ichihara from Institute of Memory Technology R&D, Kioxia Corporation, Associate Professor Shintaro Hisatake from Gifu University, Takahiro Nakamura, Ph.D. from AIO Core Co., Ltd.,
Dr. Motoaki Hara, Senior researcher from National Institute of Information and CommunicationsTechnology （NICT） , Associate Professor Katsuhiro Tomioka from Hokkaido University, for their distinguished research topics.
We look forward to all of your participation in the symposium.

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10:00	Opening remarks
	Makoto Ikeda,Professor, d.lab, school of Engineering, the University of Tokyo Yoshiaki Yoshida, President & CEO, ADVANTEST Corporation
10:10 - 11:40	Session 1 - Special Lecture I chair person：Tetsuya Iizuka d.lab, U-Tokyo
	"Measurements in millimeter-wave and THz wave band based on photonics" Shintaro Hisatake, Associate Professor Gifu University
	"High-density integrated optical transceiver based on silicon photonics technology" Takahiro Nakamura, Ph.D. AIO Core Co., Ltd.
11:40 - 13:10	lunch break
13:10 - 14:40	Sesson 2 - Sepecial Lecture II chair person：Atsutake Kosuge d.lab, U-Tokyo
	"Reliability study of ferroelectric HfO2 memory using advanced analytical techniques" Reika Ichihara Institute of Memory Technology R&D, Kioxia Corporation
	"Memristor-based echo state networks" Zhongrui Wang, Assistant Professor Department of Electrical and Electronic Engineering at the University of Hong Kong
14:40 - 14:55	15 min break
14:55 - 16:15	Session 3 - Special Lecture III chair person：Yoshio Mita d.lab, U-Tokyo
	"Vertical III-V Nanowire Transistors and Prospects" Katsuhiro Tomioka, Associate Professor Hokkaido University
	"CLIFS: Chip Level Integrated Frequency Standard, How do we approach the cliff of CLIFS? " Motoaki Hara, Senior Researcher National Institute of Information and CommunicationsTechnology （NICT）
16:15 - 16:30	Sesson 4 - Activities of D2T Research Department and Special Lecture IV
	"Activities of Advantest D2T department" Akio Higo d.lab, U-Tokyo
	Closing Tadahiro Kuroda, Director, d.lab, school of Engineering, the University of Tokyo

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Symposium abstract (日本語版, Japanese version)

"Memristor-based echo state networks" Zhongrui Wang, Assistant Professor Department of Electrical and Electronic Engineering at the University of Hong Kong The unprecedent development of Internet of Things (IoT) results in the explosion of data generated by smart edge devices, leading to a surge of interest in edge AI. This imposes a big challenge to conventional digital hardware because of physically separated memory and processing units and the transistor scaling limit. Memristors are deemed a solution for efficient and portable deep learning. However, their ionic resistive switching incurs large programming stochasticity and energy, which is detrimental to their advantages in edge AI. In this talk, we will discuss how the randomized algorithms in machine learning can enable novel hardware-software codesigns to address the aforementioned challenges. Such codesigns not only leverage the highly parallel and efficient in-memory computing with memristors, but also turn the disadvantageous stochasticity of memristors into an advantage. We will first introduce memristor-based random convolutional echo state network for spatiotemporal signal learning. Second, we will discuss how the random memristor arrays are leveraged for graph learning. Third, we will show such graph embedding, when combined with a memristive associative memory, meets the demand for few-shot graph learning.

"Reliability study of ferroelectric HfO2 memory using advanced analytical techniques" Reika Ichihara Institute of Memory Technology R&D, Kioxia Corporation

"Measurements in millimeter-wave and THz wave band based on photonics" Shintaro Hisatake, Associate Professor Gifu University

"High-density integrated optical transceiver based on silicon photonics technology" Takahiro Nakamura, Ph.D. AIO Core Co., Ltd.

"CLIFS: Chip Level Integrated Frequency Standard, How do we approach the cliff of CLIFS? " Motoaki Hara, Senior Researcher National Institute of Information and CommunicationsTechnology （NICT）

"Vertical III-V Nanowire Transistors and Prospects" Katsuhiro Tomioka, Associate Professor Hokkaido University

"Activity report of D2T research department" Akio Higo d.lab D2T research department, the University of Tokyo

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Registration (free of charge）

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D2T Symposium history

Past D2T Symposium pages

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Contact

ADVANTEST D2T Research Department,
Sysmtems Design Lab (d.lab), School of Engineering, The University of Tokyo
Room 404, Takeda Building, Yayoi 2-11-16, Bunkyo-ku, Tokyo, 113-0032, Japan
Tel: +81-3-5841-0233 FAX: +81-3-5841-1093
E-mail: higo[at]if.t.u-tokyo.ac.jp

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Systems Design Lab. (d.lab), School of Engineering, The University of Tokyo