東京大学VDEC 第13回 D2Tシンポジウム

2018年9月26日(水)
東京大学武田先端知ビル 5階武田ホール

更新情報：

・シンポジウムのホームページを開設しました。(2018/7/10)
・シンポジウムのホームページを更新しました。(2018/8/10)
・小関先生のアブストラクトを更新しました。(2018/8/14)
・参加申し込みを開始しました。(2018/8/15)
・アニエス先生のアブストラクトを更新しました。(2018/9/6)
・参加申し込みをクローズしました。当日受付を致します。

シンポジウムの概要

主催	東京大学大規模集積システム設計教育研究センター (VDEC)
後援	株式会社アドバンテスト
協賛(予定)	一般社団法人電子情報通信学会 (IEICE) 一般社団法人情報処理学会 (IPSJ) IEEE SSCS Japan Chapter IEEE SSCS Kansai Chapter 応用物理学会　集積化ＭＥＭＳ技術研究会ナノテスティング学会 (INANOT) 一般社団法人電子情報技術産業協会 (JEITA) 一般社団法人日本半導体製造装置協会 (SEAJ) SEMI ジャパン一般社団法人パワーデバイス・イネーブリング協会 (PDEA) 計測エンジニアリングシステム株式会社(KESCO)
参加費	無料
発表言語	英語。英日同時通訳あり。※英日同時通訳レシーバの数には限りがあります。

主催者より：

東京大学大規模集積システム設計教育研究センターでは、株式会社アドバンテストからの寄附による「アドバンテストD2T寄附研究部門」において、 "D2T (Design-to-Test)"の理念に基づき、「設計」と「テスト」の橋渡しを目的とした研究・教育活動を行なっています。その一環として開催して参りました「D2Tシンポジウム」の第13回目の開催を下記の通りご案内申し上げます。
今回のシンポジウムでは、海外から5名を招待講演者として米国よりSule Ozev教授、Abhijit Chatterjee教授、Adit Singh教授、香港よりK.-T. Tim Cheng教授、フランスよりGilgueng Hwang准教授をお招きし、最新の研究についての貴重な講演を頂く予定です。また、東京大学大学院工学系工学科の小関泰之先生、東京大学先端科学技術研究センターのAgnes Tixier-Mita先生にはバイオフォトニクス・バイオエレクトロニクスの最新の研究について論じて頂くことになっております。
皆様のご参加を心よりお待ち申し上げております。

シンポジウムプログラム (英語版, English version)

10:00 開会

10:15 セッション 1 - 特別講演 I ナノバイオエレクトロニクス・バイオフォトニクス

"On-chip micro/nanorobotic swimmers towards biomedical applications"
Gilgueng Hwang (CNRS, University of Paris-Saclay)

Abstract
Micro/nanorobotic swimmers can serve as alternative microfluidic tools toward biologic or biomedical applications. We aim to develop highly energy efficient and fully controllable on-chip magnetic micro/nanorobotic swimmers with remote controlled functions such as cargo transport and sensing. In this talk, I will introduce our recently developed micro/nanorobotic swimmers including their fabrications by two-photon laser 3D nanolithography, force characterizatons and their microfluidics applications. Two applications to simulate their future in-vivo and lab-on-a-chip applications are demonstrated. First, the micro/nanorobotic swimmer serves as mobile micromanipulator inside microfluidic device to transpose microscale objects. Second, we demonstrate their physical sensing applications inside microfluidic control platform.

"Large-scale biological imaging of cells with ultrafast lasers"
Yasuyuki Ozeki (Dept. of EEIS, The University of Tokyo)

Abstract
Our research aims at rapid imaging of intracellular biomolecules using ultrashort pulsed laser to find cells which are capable of highly efficient bioproduction from a large heterogeneous population of cells. In the presentation, I will introduce our research on high-speed biological imaging, and introduce various analog/digital signal processing used therein.

"Thin-Film-Transistor Technology: Display Technology for Biological Applications"
Agnes Tixier-Mita (RCAST, The University of Tokyo)

Abstract
Thin-Film-Transistor (TFT) technology has been the primary technology for liquid crystal displays (LCD) fabrication for the past 30 years. With this technology, a large array of pixels is obtained, each pixel being individually controllable by a corresponding array of TFTs. This configuration is of great interest for electrical sensing and studies of biological entities: transparent devices with a wide and dense array of microelectrodes, controlled individually by an array of TFTs can then be obtained. Our group is investigating the usage of this technology for applications as wide as cells manipulation, neurons stimulation and excitation, culture monitoring and biomolecule sensing.

12:30 昼食

14:00 セッション 2 - 特別講演 II

"Ensuring Product Quality through Design for Test for Embedded Circuits"
Sule Ozev(Arizona State University)

"Power-Performance Aware, Off-Line and On-Line Adaptation of Mixed-Signal/RF Circuits and Systems: A Machine Learning Assisted Approach"
Abhijit Chatterjee (Georgia Institute of Technology)

Abstract
Real-time systems for wireless communication, digital signal processing and control experience a wide gamut of operating conditions (signal/channel noise, workload demand, perturbed process conditions, failures). As a consequence, they need to be tuned post-manufacture and in the field to maximize performance and error-resilience while minimizing power consumption. To enable such adaptation, we propose to sense device operating conditions using built-in sensors and/or low-overhead function encoding techniques. A key capability is that of being able to deduce multiple performance parameters of the system-under-test using compact optimized stimulus. The sensors and function encodings assess the loss in performance of the relevant systems due to workload uncertainties, manufacturing process imperfections and field degradation. These are then mitigated through the use of algorithm-through-circuit level compensation techniques. A key aspect of this work is in the use of machine learning algorithms for both performance estimation and post-manufacture/in-field tuning. The key objective is to deliver end-to-end desired application level Quality of Service (QoS), while minimizing energy/power consumption across dynamically changing operating conditions. Applications to mixed-signal designs, wireless communications systems and control applications are discussed.

15:30 休憩

16:00 セッション 3 - 特別講演 III

"Hardware Security - Verification, Test, and Defense Mechanisms"
K.-T. Tim Cheng (Hong Kong University of Science and Technology)

Abstract
In this talk I will illustrate several types of Hardware Trojans and security threats they create, as well as opportunities of Trojan insertion in all steps of the design, fabrication, and testing processes. I will then discuss their defense mechanisms, verification techniques for Trojan detection and prevention, and test-specific need and challenges for hardware security.

"Are System Level Tests Unavoidable for High End Processors?"
Adit Singh (Auburn University)

Abstract
A major new test challenge encountered by industry over the past 4-5 years is the rapidly growing need for expensive system level functional tests as a final test screen for processor SOCs. Traditional low cost scan based structural tests no longer suffice in delivering acceptable defect levels in shipped product. This presentation aims at explaining why system level tests (SLTs) have become unavoidable in the test flow for complex smartphone, notebook and other processor SOCs. We take an in-depth look at the limitations of traditional low cost scan based test methodology that appear to necessitate the use of functional SLTs as an additional final test screen. We then consider possible improvements to structural test that may mitigate these shortcomings and minimize the need for SLTs.

17:30 セッション 4 - VDEC D2T寄附研究部門

"Activities of D2T research division"
Akio Higo (VDEC D2T, The University of Tokyo)

17:45 閉会

18:00 懇親会

参加申込（参加費：無料）

本シンポジウムは終了いたしました。どうもありがとうございました。

アクセス方法

こちらをご覧ください。

D2T シンポジウムの歴史

過去の D2T シンポジウムのウェブページ

お問い合わせ

肥後昭男
東京大学大規模集積システム設計教育研究センターアドバンテストD2T寄附研究部門
〒113－0032　東京都文京区弥生2－11－16　武田先端知ビル404号室
Tel: 03-5841-0233 FAX: 03-5841-1093
E-mail: higo[at]if.t.u-tokyo.ac.jp

VLSI Design and Education Center (VDEC), The University of Tokyo

10:00	開会
10:15	セッション 1 - 特別講演 I ナノバイオエレクトロニクス・バイオフォトニクス
	"On-chip micro/nanorobotic swimmers towards biomedical applications" Gilgueng Hwang (CNRS, University of Paris-Saclay)
	Abstract Micro/nanorobotic swimmers can serve as alternative microfluidic tools toward biologic or biomedical applications. We aim to develop highly energy efficient and fully controllable on-chip magnetic micro/nanorobotic swimmers with remote controlled functions such as cargo transport and sensing. In this talk, I will introduce our recently developed micro/nanorobotic swimmers including their fabrications by two-photon laser 3D nanolithography, force characterizatons and their microfluidics applications. Two applications to simulate their future in-vivo and lab-on-a-chip applications are demonstrated. First, the micro/nanorobotic swimmer serves as mobile micromanipulator inside microfluidic device to transpose microscale objects. Second, we demonstrate their physical sensing applications inside microfluidic control platform.
	"Large-scale biological imaging of cells with ultrafast lasers" Yasuyuki Ozeki (Dept. of EEIS, The University of Tokyo)
	Abstract Our research aims at rapid imaging of intracellular biomolecules using ultrashort pulsed laser to find cells which are capable of highly efficient bioproduction from a large heterogeneous population of cells. In the presentation, I will introduce our research on high-speed biological imaging, and introduce various analog/digital signal processing used therein.
	"Thin-Film-Transistor Technology: Display Technology for Biological Applications" Agnes Tixier-Mita (RCAST, The University of Tokyo)
	Abstract Thin-Film-Transistor (TFT) technology has been the primary technology for liquid crystal displays (LCD) fabrication for the past 30 years. With this technology, a large array of pixels is obtained, each pixel being individually controllable by a corresponding array of TFTs. This configuration is of great interest for electrical sensing and studies of biological entities: transparent devices with a wide and dense array of microelectrodes, controlled individually by an array of TFTs can then be obtained. Our group is investigating the usage of this technology for applications as wide as cells manipulation, neurons stimulation and excitation, culture monitoring and biomolecule sensing.
12:30	昼食
14:00	セッション 2 - 特別講演 II
	"Ensuring Product Quality through Design for Test for Embedded Circuits" Sule Ozev(Arizona State University)
	"Power-Performance Aware, Off-Line and On-Line Adaptation of Mixed-Signal/RF Circuits and Systems: A Machine Learning Assisted Approach" Abhijit Chatterjee (Georgia Institute of Technology)
	Abstract Real-time systems for wireless communication, digital signal processing and control experience a wide gamut of operating conditions (signal/channel noise, workload demand, perturbed process conditions, failures). As a consequence, they need to be tuned post-manufacture and in the field to maximize performance and error-resilience while minimizing power consumption. To enable such adaptation, we propose to sense device operating conditions using built-in sensors and/or low-overhead function encoding techniques. A key capability is that of being able to deduce multiple performance parameters of the system-under-test using compact optimized stimulus. The sensors and function encodings assess the loss in performance of the relevant systems due to workload uncertainties, manufacturing process imperfections and field degradation. These are then mitigated through the use of algorithm-through-circuit level compensation techniques. A key aspect of this work is in the use of machine learning algorithms for both performance estimation and post-manufacture/in-field tuning. The key objective is to deliver end-to-end desired application level Quality of Service (QoS), while minimizing energy/power consumption across dynamically changing operating conditions. Applications to mixed-signal designs, wireless communications systems and control applications are discussed.
15:30	休憩
16:00	セッション 3 - 特別講演 III
	"Hardware Security - Verification, Test, and Defense Mechanisms" K.-T. Tim Cheng (Hong Kong University of Science and Technology)
	Abstract In this talk I will illustrate several types of Hardware Trojans and security threats they create, as well as opportunities of Trojan insertion in all steps of the design, fabrication, and testing processes. I will then discuss their defense mechanisms, verification techniques for Trojan detection and prevention, and test-specific need and challenges for hardware security.
	"Are System Level Tests Unavoidable for High End Processors?" Adit Singh (Auburn University)
	Abstract A major new test challenge encountered by industry over the past 4-5 years is the rapidly growing need for expensive system level functional tests as a final test screen for processor SOCs. Traditional low cost scan based structural tests no longer suffice in delivering acceptable defect levels in shipped product. This presentation aims at explaining why system level tests (SLTs) have become unavoidable in the test flow for complex smartphone, notebook and other processor SOCs. We take an in-depth look at the limitations of traditional low cost scan based test methodology that appear to necessitate the use of functional SLTs as an additional final test screen. We then consider possible improvements to structural test that may mitigate these shortcomings and minimize the need for SLTs.
17:30	セッション 4 - VDEC D2T寄附研究部門
	"Activities of D2T research division" Akio Higo (VDEC D2T, The University of Tokyo)
17:45	閉会
18:00	懇親会