The 16th D2T Symposium, The University of Tokyo
September 15th (Wed.), 2021
Virtual Conference @ Zoom
(日本語版, Japanese page)
News：
- Symposium homepage was opened. (2021/7/16)
- Registration started. (2021/7/30)
- The seminar is closed. (2021/9/15)
Symposium Overview
Organizer
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Sponsor
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Supporters
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Admission fee
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Not required
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Presentation Language
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English
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From the organizer:
"D2T Symposium" will be held on 15th September, 2021, as
16th meeting of symposium series first started in 2008.
We have been pursuing in "design", "test", and their bridging technologies
in the symposia as indicated in the name "D2T" that means "Design to Test".
This year, we will invite lecturers overseas, Professor Wayne Luk from Imperial College London, Professor Mehdi Tahoori from Dependable Nano-Computing at Karlsruhe Institute of Technology, Professor Alex Orailoglu from University of California, San Diego,
Professor and U-Tokyo fellow, K.-T. Tim Cheng from Hong Kong University of Science and Technology, Dr. Shin-ichi O'uchi (S. O'uchi) from AIST-UTokyo AI Chip Design Open Innovation Laboratory (AIDL), National Institute of Advanced Industrial Science and Technology (AIST)
Professor Tadahiro Kuroda from d.lab, the University of Tokyo and Professor Teruo Fujii, Director, The University of Tokyo, for their distinguished research topics.
We look forward to all of your participation in the symposium.
10:00
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Opening remarks
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Tadahiro Kuroda, Director, d.lab, school of Engineering, the University of Tokyo
Yoshiaki Yoshida, President & CEO, ADVANTEST Corporation
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10:15 - 11:55
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Session 1 - Special Lecture I
Chair persons: Yoshio Mita (d.lab, the University of Tokyo) and Masahiro Fujita (d.lab, the University of Tokyo)
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"Microfluidics for Cellular and Molecular Systems"
Teruo Fujii, Professor (the University of Tokyo)
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10 min break
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"Meta-programming Strategies for Multi-Target Design Optimisation"
Wayne Luk, Professor (Imperial College London)
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11:55 - 13:00
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Lunch Break
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>
13:00 - 14:30
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Sesson 2 - Sepecial Lecture II
Chair person: Tetsuya Iizuka (d.lab, the University of Tokyo)
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"Time Performance Improvement by Agile Design and 3D Integration"
Tadahiro Kuroda (The University of Tokyo)
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"Design of Reliable and Efficient Deep Learning Processing Systems"
Alex Orailoglu, Professor
(University of California, San Diego)
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14:30 - 14:45
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15 min break
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14:45 - 16:15
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Session 3 - Special Lecture III
Chair person: Makoto Ikeda (d.lab, the University of Tokyo)
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"Ratio based Resistive Memory Cells for Low Error Rate and High Energy Efficiency"
K.-T. Tim Cheng, Professor U-Tokyo Fellow
(Hong Kong University of Science and Technology)
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"AI-Accelerator Proof of Concept by a Multi-IP Chip Project"
Shin-ichi O'uchi (S. O'uchi) Laboratory Team Leader, AIST-UTokyo AI Chip Design Open Innovation Laboratory
(AIDL)
National Institute of Advanced Industrial Science and Technology (AIST)
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16:15 - 16:30
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15 min break
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16:30 -
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Sesson 4 - Activities of D2T Research Department and Special Lecture IV
Chair person: Masahiro Fujita (d.lab, the University of Tokyo)
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"Activities of D2T research department"
Akio Higo d.lab, The University of TOkyo
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"Analysis and Calibration Techniques of Modulated Wideband Converter
for High-Precision Sub-Nyquist Sampling System"
Zolboo Byambadorj, Doctoral research fellow,
d.lab, The University of Tokyo
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"Computing Paradigms based on Flexible Inorganic Printed Electronics"
Mehdi Tahoori, Professor
Dependable Nano-Computing at Karlsruhe Institute of Technology
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"Microfluidics for Cellular and Molecular Systems"
Teruo Fujii, Professor
Director, The University of Tokyo
As one of the spin-out research areas based on semiconductor microfabrication technologies, microfluidics have emerged since 1990s. I would like to highlight cellular and molecular systems using microfluidic techniques and to discuss on how we can further expand the horizon of this technology.
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"Meta-programming Strategies for Multi-Target Design Optimisation"
Wayne Luk, Professor
Imperial College London
This talk describes recent research on meta-programming techniques for mapping high-level descriptions to multiple hardware platforms. The purpose is to enhance design productivity and maintainability. Our approach is based on decoupling functional concerns from optimisation concerns, allowing separate descriptions to be independently maintained by two types of experts: application experts focus on algorithmic behaviour, while platform experts focus on the mapping process. Our approach supports both customisable optimisations to rapidly capture a wide range of mapping strategies targeting multiple hardware platforms, and reusable strategies to allow optimisations to be described once and applied to multiple applications. Examples will be provided to illustrate how the proposed approach can map a single high-level program into multi-core processors and reconfigurable hardware platforms.
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"Time Performance Improvement by Agile Design and 3D Integration"
Tadahiro Kuroda, Professor
d.lab, The University of Tokyo
In this presentation, the use of an agile design methodology enabled
by high-capacity SRAM and silicon compiler technology, as well as 3D
IC integration to improve IC time-performance will be described.
Furthermore, cost and performance analysis and comparison with current
solutions especially in base station applications will be presented.
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"Ratio based Resistive Memory Cells for Low Error Rate and High Energy Efficiency"
K.-T. Tim Cheng, Professor
U-Tokyo Fellow, and Hong Kong University of Science and Technology
We present the concept and mechnisim of ratio-based encoding for ReRAM memory cells, in which the resistance ratio of a pair of resistance-switching devices, rather than the resistance of a single device (i.e. resistance-based encoding), is used for encoding the information, which significantly reduces the bit error probability and/or the write energy.
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"AI-Accelerator Proof of Concept by a Multi-IP Chip Project"
Shin-ichi O'uchi (S. O'uchi)
Laboratory Team Leader, AIST-UTokyo AI Chip Design Open Innovation Laboratory
(AIDL)
National Institute of Advanced Industrial Science and Technology (AIST)
In this talk, implementation of an AI accelerator by a multi-IP chip project of AI-Chip Design Center, a joint project of AIST and University of Tokyo, is reviewed. The accelerator core design to exhaustively process the data flow from the DDR in the chip platform, is also presented.
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"Computing Paradigms based on Flexible Inorganic Printed Electronics"
Mehdi Tahoori, Professor
Dependable Nano-Computing at Karlsruhe Institute of Technology
Flexible electronics is an emerging and fast growing field which can be used in many demanding and emerging application domains such as wearables, smart sensors, and Internet of Things (IoT). Unlike traditional computing and electronics domain which is mostly driven by performance characteristics, flexible electronics based on additive manufacturing processes are mainly associated with low fabrication costs (as they are used even in consumer market) and low energy consumption (as they could be used in energy-harvested systems). Printed electronics offer certain technological advantages over their silicon based counterparts, like mechanical flexibility, low process temperatures, maskless and additive manufacturing possibilities. However, it is essential that the printed devices operate at low supply voltages. Electrolyte gated transistors (EGTs) using solution-processed inorganic materials which are fully printed using inkject printers at low temperatures are very promising to provide such solutions. In this talk, I discuss the technology, process, modeling, fabrication, design (automation), computing paradigms and security aspects of circuits based on additive printed technologies.
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"Design of Reliable and Efficient Deep Learning Processing Systems"
Alex Orailoglu, Professor
University of California, San Diego
The talk outlines a path for utilizing the inherent plasticity, resiliency, and redundancy of deep learning algorithms to deliver dramatic boosts in functional safety and resource efficiency. The method embeds strong reliability characteristics in safety-critical deep learning applications at negligible cost and offers a promising approach to improve resource efficiency.
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"Analysis and Calibration Techniques of Modulated Wideband Converter
for High-Precision Sub-Nyquist Sampling System"
Zolboo Byambadorj, Doctoral research fellow
d.lab, The University of Tokyo
TBD
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"Activities of Advantest D2T Research Department"
Akio Higo
D2T Research Department,d.lab, The University of Tokyo
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D2T Symposium history
Past D2T Symposium pages
Contact
ADVANTEST D2T Research Department,
Sysmtems Design Lab (d.lab), School of Engineering, The University of Tokyo
Room 404, Takeda Building,
Yayoi 2-11-16, Bunkyo-ku, Tokyo, 113-0032, Japan
Tel: +81-3-5841-0233 FAX: +81-3-5841-1093
E-mail: higo[at]if.t.u-tokyo.ac.jp
Systems Design Lab. (d.lab), School of Engineering, The University of Tokyo